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Volumn , Issue , 2006, Pages 363-368

High-performance and parameterized matrix factorization on FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL FLUID DYNAMICS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY;

EID: 46249103564     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311238     Document Type: Conference Paper
Times cited : (21)

References (15)
  • 1
    • 2442575887 scopus 로고    scopus 로고
    • An FPGA Implementation of the Two-Dimensional FiniteDifference Time-Domain (FDTD) Algorithm
    • February
    • W. Chen and P. Kosmas and M. Leeser and C. Rappaport, "An FPGA Implementation of the Two-Dimensional FiniteDifference Time-Domain (FDTD) Algorithm," in Proc. of the FPGA 2004, February 2004.
    • (2004) Proc. of the FPGA 2004
    • Chen, W.1    Kosmas, P.2    Leeser, M.3    Rappaport, C.4
  • 2
    • 33845423995 scopus 로고    scopus 로고
    • High Performance Linear Algebra Operations on Reconfigurable Systems
    • November
    • L. Zhuo and V. K. Prasanna, "High Performance Linear Algebra Operations on Reconfigurable Systems," in Proc. of SuperComputing 2005, November 2005.
    • (2005) Proc. of SuperComputing 2005
    • Zhuo, L.1    Prasanna, V.K.2
  • 3
    • 46249094063 scopus 로고    scopus 로고
    • SRC Computers, Inc
    • SRC Computers, Inc., "http://www. srccomp.com/."
  • 4
    • 46249086923 scopus 로고    scopus 로고
    • Cray Inc
    • Cray Inc., "http://www.cray.com/."
  • 6
    • 46249129818 scopus 로고    scopus 로고
    • Efficient FloatingPoint Based Block LU Decomposition on FPGAs
    • June
    • G. Govindu, S. Choi, and V. K. Prasanna, "Efficient FloatingPoint Based Block LU Decomposition on FPGAs," in Proc. of ERSA 2004, June 2004.
    • (2004) Proc. of ERSA 2004
    • Govindu, G.1    Choi, S.2    Prasanna, V.K.3
  • 8
    • 46249092997 scopus 로고    scopus 로고
    • Xilinx Incorporated
    • Xilinx Incorporated, "http://www.xilinx.com."
  • 12
    • 67649222053 scopus 로고    scopus 로고
    • Time and Energy Efficient Matrix Factorization using FPGAs
    • September
    • S. Choi and V. K. Prasanna, "Time and Energy Efficient Matrix Factorization using FPGAs," in Proc. of FPL 2003, September 2003.
    • (2003) Proc. of FPL 2003
    • Choi, S.1    Prasanna, V.K.2
  • 13
    • 84946069788 scopus 로고    scopus 로고
    • Performance Optimization of an FPGA-Based Configurable Multiprocessor for Matrix Operations
    • December
    • X. Wang and S. G. Ziavras, "Performance Optimization of an FPGA-Based Configurable Multiprocessor for Matrix Operations," in Proc. of FPT2003, December 2003.
    • (2003) Proc. of FPT2003
    • Wang, X.1    Ziavras, S.G.2
  • 14
    • 46249119043 scopus 로고    scopus 로고
    • Mentor Graphics Corp
    • Mentor Graphics Corp., "http://www.mentor.com/."
  • 15
    • 60749122141 scopus 로고    scopus 로고
    • A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing
    • June
    • G. Govindu, R. Scrofano, and V. K. Prasanna, "A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing," in Proc. of ERSA 2005, June 2005.
    • (2005) Proc. of ERSA 2005
    • Govindu, G.1    Scrofano, R.2    Prasanna, V.K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.