Optimizing explicit data transfers for data parallel applications on the cell architecture

Transactions on Architecture and Code Optimization

Volumn 8, Issue 4, 2012, Pages

  Saidi, Selma ^a,b   Tendulkar, Pranav ^a   Lepley, Thierry ^b   Maler, Oded ^a,c  

^a UNIV GRENOBLE ALPES   (France)

^b STMICROELECTRONICS   (France)

^c VERIMAG   (France)

Author keywords

Cell B.E.; Data parallelization; Direct memory access (DMA); Double buffering

Indexed keywords

CELL ARCHITECTURES; CELL BROADBAND ENGINE ARCHITECTURE; COMPUTATION TIME; CYCLE-ACCURATE SIMULATORS; DATA ITEMS; DATA PARALLEL; DATA PARALLELIZATION; DATA SHARING; DIRECT MEMORY ACCESS; DOUBLE BUFFERING; GENERAL APPROACH; LOCAL MEMORIES; MULTI CORE; NUMBER OF BLOCKS; OFF-CHIP; OPTIMAL VALUES;

DATA TRANSFER; OPTIMIZATION;

COMPUTER ARCHITECTURE;

EID: 84857823732     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2086696.2086716     Document Type: Article

References (36)

1. AGARWAL, A., KRANZ, D., AND NATARAJAN, V. 1995. Automatic partitioning of parallel loops and data arrays for distributed shared-memory multiprocessors. IEEE Trans. Parall. Distrib. Syst. 6, 9, 943-962.
2. AGGARWAL, A., ALPERN, B., CHANDRA, A., AND SNIR, M. 1987. A model for hierarchical memory. In Proceedings of the 19th Annual ACM Symposium on Theory of Computing (STOC'87). ACM, New York, NY, 305-314.
3. AHMED, M., AMMAR, R., AND RAJASEKARAN, S. 2008. Spenk: adding another level of parallelism on the cell broadband engine. In Proceedings of the 1st International Forum on Next-Generation Multicore/Manycore Technologies. ACM, 1-10.
4. BAI, S., ZHOU, Q., ZHOU, R., AND LI, L. 2008. Barrier synchronization for cell multi-processor architecture. In Proceedings of the 1st IEEE International Conference on Ubi-Media Computing. 155-158.
5. BELTRAN, V., CARRERA, D., TORRES, J., AND AYGUADÉ, E. 2009. CellMT: A cooperative multithreading library for the Cell/BE. In Proceedings of the International Conference on High Performance Computing (HiPC). IEEE, 245-253.
6. BLAGOJEVIC, F., FENG, X., CAMERON, K. W., AND NIKOLOPOULOS, D. S. 2008. Modeling multigrain parallelism on heterogeneous multi-core processors: a case study of the cell be. In Proceedings of the 3rd International Conference on High Performance Embedded Architectures and Compilers (HiPEAC'08). Springer-Verlag, Berlin, 38-52.
7. CALLAHAN, D., KENNEDY, K., AND PORTERFIELD, A. 1991. Software prefetching. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV). ACM, New York, NY, 40-52. (Pubitemid 21702169)
8. CARPENTER, P., RAMIREZ, A., AND AYGUAD, E. 2010. Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors. In High Performance Embedded Architectures and Compilers, Y. Patt, P. Foglia, E. Duesterwald, P. Faraboschi, and X. Martorell, Eds., Lecture Notes in Computer Science Series, vol. 5952, Springer Berlin, 96-110.
9. CHEN, T., SURA, Z., O'BRIEN, K., AND O'BRIEN, J. K. 2007. Optimizing the use of static buffers for dma on a cell chip. In Proceedings of the 19th International Conference on Languages and Compilers for Parallel Computing (LCPC'06). Springer-Verlag, Berlin, 314-329.
10. CHEN, T.-F. AND BAER, J.-L. 1994. A performance study of software and hardware data prefetching schemes. SIGARCH Comput. Archit. News 22, 223-232.
11. COLEMAN, S. AND MCKINLEY, K. S. 1995. Tile size selection using cache organization and data layout. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'95). ACM, New York, NY, 279-290.
12. CULLER, D., KARP, R., PATTERSON, D., SAHAY, A., SCHAUSER, K. E., SANTOS, E., SUBRAMONIAN, R., AND VON EICKEN, T. 1993. LogP: Towards a realistic model of parallel computation. In Proceedings of the 4th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP'93). ACM, New York, NY, 1-12.
13. DAHLGREN, F., DUBOIS, M., AND STENSTRÖM, P. 1995. Sequential hardware prefetching in shared-memory multiprocessors. IEEE Trans. Parall. Distrib. Syst. 6, 733-746.
14. ESSEGHIR, K. 1993. Improving data locality for caches. Master's thesis, Department of Computer Science, Rice University.
15. FATAHALIAN, K., HORN, D., KNIGHT, T., LEEM, L., HOUSTON, M., PARK, J., EREZ, M., REN, M., AIKEN, A., DALLY, W., ET AL. 2006. Sequoia: Programming the memory hierarchy. In Proceedings of the ACM/IEEE Conference on Supercomputing.
16. FRITTS, J. 2002. Multi-level memory prefetching for media and stream processing. In Proceedings of the IEEE International Conference on Multimedia and Expo (ICME '02). vol. 2, 101-104.
17. FU CHEN, T. AND LOUP BAER, J. 1995. Effective hardware-based data prefetching for high-performance processors. IEEE Trans. Comput. 44, 609-623.
18. GSCHWIND, M. 2007. The cell broadband engine: exploiting multiple levels of parallelism in a chip multiprocessor. Int. J. Parall. Program. 35, 3, 233-262. (Pubitemid 46904453)
19. IBM. 2008. Cell SDK 3.1. https://www.ibm.com/developerworks/power/cell/.
20. IBM. 2009. Cell Simulator. http://www.alphaworks.ibm.com/tech/ cellsystemsim.
21. KISTLER, M., PERRONE, M., AND PETRINI, F. 2006. Cell multiprocessor communication network: Built for speed. IEEE Micro, 26, 3, 10-23. (Pubitemid 44194065)
22. LAM, M. D., ROTHBERG, E. E., AND WOLF, M. E. 1991. The cache performance and optimizations of blocked algorithms. SIGOPS Oper. Syst. Rev. 25, 63-74.
23. MOWRY, T. AND GUPTA, A. 1991. Tolerating latency through software-controlled prefetching in shared-memory multiprocessors. J. Parall. Distrib. Comp. 12, 87-106.
24. NUSSBAUMER, H. J. 1981. Fast Fourier Transform and Convolution Algorithms. Springer-Verlag, Berlin.
25. PETRINI, F., FOSSUM, G., FERNANDEZ, J., VARBANESCU, A., KISTLER, M., AND PERRONE, M. 2007. Multicore surprises: Lessons learned from optimizing sweep3d on the cell broadband engine. In Proceedings of IPDPS'07. IEEE, 1-10.
26. PHAM, D., ANDERSON, H.-W., BEHNEN, E., BOLLIGER, M., GUPTA, S., HOFSTEE, H. P., HARVEY, P. E., JOHNS, C. R., KAHLE, J. A., KAMEYAMA, A., KEATY, J. M., LE, B., LEE, S., NGUYEN, T. V., PETROVICK, J. G., PHAM, M., PILLE, J., POSLUSZNY, S. D., RILEY, M. W., VEROCK, J., WARNOCK, J. D., WEITZEL, S., AND WENDEL, D. F. 2006. Key features of the design methodology enabling a multi-core soc implementation of a first-generation cell processor. In Proceedings of ASP-DAC. F. Hirose, Ed., IEEE, 871-878. (Pubitemid 44376041)
27. SANCHO, J. AND KERBYSON, D. 2008. Analysis of double buffering on two different multicore architectures: Quad-core Opteron and the Cell-BE. In IPDPS 2008. Proceedings of the IEEE International Symposium on Parallel and Distributed Processing. IEEE.
28. SANCHO, J. C., BARKER, K. J., KERBYSON, D. J., AND DAVIS, K. 2006. Quantifying the potential benefit of overlapping communication and computation in large-scale scientific applications. In Proceedings of the ACM/IEEE Conference on Supercomputing (SC'06). ACM, New York, NY.
29. SCHNEIDER, S., YEOM, J., AND NIKOLOPOULOS, D. 2009. Programming multiprocessors with explicitly managed memory hierarchies. Computer 42, 12, 28-34.
30. SCHNEIDER, S., YEOM, S., ROSE, B., LINFORD, J., SANDU, A., AND NIKOLOPOULOS, D. 2009. A comparison of programming models for multiprocessors with explicitly managed memory hierarchies. ACM SIGPLAN Notices.
31. STMICROELECTRONICS AND CEA. 2010. Platform 2012: Amany core programmable accelerator for ultra efficient embedded computing in nanometer technology.
32. SUDHEER, C., NAGARAJU, T., BARUAH, P., AND SRINIVASAN, A. 2009. Optimizing assignment of threads to spes on the cell be processor. In Proceedings of the International Parallel and Distributed Processing Symposium. 0, 1-8.
33. VALIANT, L. G. 1990. A bridging model for parallel computation. Comm. ACM 33, 103-111.
34. WANG, Z., BURGER, D., MCKINLEY, K. S., REINHARDT, S. K., AND WEEMS, C. C. 2003. Guided region prefetching: a cooperative hardware/software approach. SIGARCH Comput. Archit. News 31, 388-398.
35. WOLFE, M. 1989. More iteration space tiling. In Proceedings of the ACM/IEEE Conference on Supercomputing (Supercomputing '89). ACM, New York, NY, 655-664. (Pubitemid 20665965)
36. ZINNER, C. AND KUBINGER, W. 2006. Ros-dma: A dma double buffering method for embedded image processing with resource optimized slicing. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium. 361-372. (Pubitemid 44539785)