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Volumn 4382 LNCS, Issue , 2007, Pages 314-329

Optimizing the use of static buffers for DMA on a CELL chip

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; MATHEMATICAL MODELS; PROGRAM COMPILERS;

EID: 38149004865     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-72521-3_23     Document Type: Conference Paper
Times cited : (31)

References (13)
  • 4
    • 27344435504 scopus 로고    scopus 로고
    • The design and implementation of a first-generation CELL processor
    • February
    • D. Pham et al. The design and implementation of a first-generation CELL processor. IEEE International Solid-State Circuits Conference, February 2005.
    • (2005) IEEE International Solid-State Circuits Conference
    • Pham, D.1
  • 5
    • 38049183918 scopus 로고    scopus 로고
    • European Center for Parallelism of Barcelona CEPBA, manual. November, URL
    • European Center for Parallelism of Barcelona (CEPBA). Paraver: Parallel program visualization and analysis tool reference manual. November 2000. URL: http://www.cepba.upc.es/paraver.
    • (2000) Paraver: Parallel program visualization and analysis tool reference
  • 11
    • 33746923043 scopus 로고    scopus 로고
    • CELL multiprocessor communication network: Built for speed
    • May/June
    • M. Kistler, M. Perrone, and F. Petrini. CELL multiprocessor communication network: Built for speed. IEEE Micro, 26(3), May/June 2006.
    • (2006) IEEE Micro , vol.26 , Issue.3
    • Kistler, M.1    Perrone, M.2    Petrini, F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.