The cell broadband engine: Exploiting multiple levels of parallelism in a chip multiprocessor

International Journal of Parallel Programming

Volumn 35, Issue 3, 2007, Pages 233-262

  Gschwind, Michael ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Cell Broadband Engine; Chip multiprocessor; Compute transfer parallelism; Heterogeneous chip multiprocessor; Multi level application parallelism

Indexed keywords

CELL BROADBAND ENGINE; CHIP MULTIPROCESSORS; COMPUTE-TRANSFER PARALLELISM; HETEROGENEOUS CHIP MULTIPROCESSORS; MEMORY LATENCY; MULTI-LEVEL APPLICATION PARALLELISM; SYNERGISTIC PROCESSOR ELEMENT (SPE);

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; MULTIPROCESSING SYSTEMS; SCHEDULING;

SEARCH ENGINES;

EID: 34250167228     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10766-007-0035-4     Document Type: Article

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