Hybrid floating gate cell for sub-20-nm NAND flash memory technology

IEEE Electron Device Letters

Volumn 33, Issue 3, 2012, Pages 333-335

  Blomme, P ^a   Cacciato, A ^a   Wellekens, D ^a   Breuil, L ^a   Rosmeulen, M ^a   Kar, G S ^a   Locorotondo, S ^a   Vrancken, C ^a   Richard, O ^a   Debusschere, I ^a   Van Houdt, J ^a  

^a IMEC   (Belgium)

Author keywords

Cell integration; dual layer floating gate (FG); nand flash memory scaling

Indexed keywords

CELL INTEGRATION; CYCLING ENDURANCE; DATA RETENTION; DUAL LAYER; FLOATING GATES; FULLY INTEGRATED; HIGH POTENTIAL; MEMORY CELL; NAND FLASH MEMORY; PROGRAM PERFORMANCE; PROGRAM/ERASE; ROADMAP; TECHNOLOGY NODES; VIABLE SOLUTIONS;

CYTOLOGY; NAND CIRCUITS;

FLASH MEMORY;

EID: 84857445725     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2181152     Document Type: Article

References (13)

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