Novel dual layer floating gate structure as enabler of fully planar flash memory

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 129-130

  Blomme, Pieter ^a   Rosmeulen, Maarten ^a   Cacciato, Antonio ^a   Kostermans, Maarten ^a   Vrancken, Christa ^a   Van Aerde, Steven ^b   Schram, Tom ^a   Debusschere, Ingrid ^a   Jurczak, Malgorzata ^a   Van Houdt, Jan ^a  

^a IMEC   (Belgium)

^b ASM   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLING PERFORMANCE; DATA RETENTION; DUAL LAYER; FLOATING GATE MEMORIES; FLOATING GATES; FLOATING-GATE STRUCTURES; K -CYCLE; PLANAR CELLS; WORDLINES;

FLASH MEMORY;

EID: 77957880275     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556198     Document Type: Conference Paper

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