Redundant vias insertion for performance enhancement in 3D ICs

IEICE Transactions on Electronics

Volumn E91-C, Issue 4, 2008, Pages 571-580

  Zhang, Xu ^a   Jiang, Xiaohong ^a   Horiguciu, Susumu ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

3D IC; Delay; Impedance matching; Redundant vim; Signal integrity; Via placement

Indexed keywords

BUSBARS; IMPEDANCE MATCHING (ELECTRIC); THREE DIMENSIONAL INTEGRATED CIRCUITS; TIMING CIRCUITS;

65 NM CMOS TECHNOLOGIES; DELAY; PERFORMANCE ENHANCEMENTS; REDUNDANT VIA INSERTION; REDUNDANT VIM; SIGNAL INTEGRITY; THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS; VIA PLACEMENTS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 77953566254     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e91-c.4.571     Document Type: Article

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