On-chip bus signaling using passive compensation

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2008, Pages 33-36

  Zhang, Yulei ^a   Zhang, Ling ^b   Deutsch, Alina ^c   Katopis, George A ^d   Dreps, Daniel M ^d   Buckwalter, James F ^a   Kuh, Ernest S ^e   Cheng, Chung Kuan ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d IBM   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGIES; CASE STUDIES; CROSSTALK EFFECTS; GLOBAL WIRES; LOSSY TRANSMISSION LINES; ON CHIPS; PASSIVE COMPENSATIONS; PERFORMANCE LIMITATIONS; POWER EFFICIENCIES; PREDICTION ALGORITHMS; SEQUENTIAL QUADRATIC PROGRAMMINGS; TRANSMISSION SPEEDS;

ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; SEQUENTIAL SWITCHING;

CHIP SCALE PACKAGES;

EID: 58049109938     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2008.4675869     Document Type: Conference Paper

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