Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

Microelectronics Reliability

Volumn 50, Issue 9-11, 2010, Pages 1636-1640

  Yang, Y ^a,b   Labie, R ^a   Ling, F ^a,b   Zhao, C ^c   Radisic, A ^a   Van Olmen, J ^a   Travaly, Y ^a   Verlinden, B ^b   De Wolf, I ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

3D ARCHITECTURES; BARRIER THICKNESS; CRITICAL COMPONENT; DILUTE HF; FABRICATION PROCESS; FOUR-POINT BENDING; FRACTOGRAPHIC ANALYSIS; INTERFACIAL ADHESIONS; NONUNIFORMITY; QUANTITATIVE ASSESSMENTS; RELIABILITY TEST; SCANNING ELECTRON MICROSCOPIC; SEED LAYER; SIDEWALL ROUGHNESS; THERMAL CYCLING TEST; THROUGH SILICON VIAS;

RELIABILITY ANALYSIS; THREE DIMENSIONAL;

ADHESION;

EID: 84355166174     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.07.019     Document Type: Conference Paper

References (20)

1. S. Borkar 3D integration for energy efficient system design VLSI Technol 2009 58 59
2. W. Haensch Why should we do 3D integration? DAC 2008 674 675
3. E. Beyne The rise of the 3rd dimension for system integration IITC 2006 1 5
4. J. Van Olmen 3D stacked IC demonstration using a through silicon via first approach IEDM 2008 603 606
5. H.H. Chang 3D stacked chip technology using bottom-up electroplated TSVs ECTC 2009 1177 1184
6. E.M. Chow Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates J MEMS 11 2002 631 640
7. G. Katti 3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding IEDM 2009 357 360
8. Y.S. Kim Ultra thinning 300-mm wafer down to 7-μm for 3D wafer integration on 45-nm node CMOS using strained silicon and Cu/low-k interconnects IEDM 2009 365 368
9. K.L. Mittal Adhesion measurement of thin film Electrocompon Sci Technol 3 1976 21 42
10. M.J. Matthewson Adhesion measurement of thin films by indentation Appl Phys Lett 49 1986 1426 1428
11. R.H. Dauskardt, M. Lane, Q. Ma, and N. Krishna Adhesion and debonding of multilayer thin film structures Eng Fract Mech 61 1998 141 162
12. W.W. Gerberich, and M.J. Cordill Physics of adhesion Report Prog Phys 69 2006 2157 2203
13. F. Raynal Electrografted seed layers for metallization of deep TSV structures ECTC 2009 1147 1152
14. B. Swinnen 3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias IEDM 2006 1 371 374
15. Degryse D. Experimental and finite element study of stress concentration in thin film layer structures for electronic packaging. PhD dissertation, Gent Universiteit, Belgium; 2006.
16. C. Laviron Via first approach optimisation for through silicon via applications ECTC 2009 14 19
17. Larmer F, Schilp A. A method of anisotropically etching silicon, US Patent Specification 5501893, German Patent Specification DE4241045.
18. M. Puech Fabrication of 3D packaging using DRIE DTIP 2008 109 114
19. K.L. Mittal Adhesion aspects of metallization of organic polymer surfaces J Vac Sci Technol 13 1976 19 25
20. Ge J. Interfacial adhesion in metal/polymer systems for electronics. PhD dissertation, Helsinki University of Technology, Finland; 2003.