Bus-driven floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 11, 2004, Pages 1522-1530

  Xiang, Hua ^a   Tang, Xiaoping ^b   Wong, Martin D F ^c  

^a CADENCE DESIGN SYSTEMS   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

Computer aided design (CAD); Floorplan; Physical design; Sequence pair; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; FLOORS; MICROPROCESSOR CHIPS; OPTIMIZATION; PLANNING; ROUTERS;

BUS-DRIVEN FLOORPLANNING (BDF); FLOORPLAN; PHYSICAL DESIGN; SEQUENCE PAIR;

VLSI CIRCUITS;

EID: 8344272834     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.836728     Document Type: Article

References (8)

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2. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1518-1524, Dec. 1996.
3. F. Rafiq, M. Chrzanowska-Jeske, H. H. Yang, and N. Sherwani, "Bus-based integrated floorplanning," in Proc. IEEE Int. Symp. Circuits Syst., 2002, pp. 875-878.
4. _, "Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs," Proc. Int. Symp. Phys. Design, pp. 56-61, 2002.
5. X. Tang, R. Tian, and D. F. Wong, "Fast evaluation of sequence pair in block placement by longest common subsequence computation," Proc. Design Automation Test Eur., pp. 106-111, 2000.
6. X. Tang and D. F. Wong, "FAST-SP: A fast algorithm for block placement based sequence pair," Proc. ASPDAC, pp. 521-526, 2001.
7. X. Tang and D. F. Wong, "Floorplanning with alignment and performance constraints," Proc. DAC, pp. 848-853, June 2002.
8. F. Y. Young, C. N. Chu, and M. L. Ho, "A unified method to handle different kinds of placement constraints in floorplan design," in Proc. 15th Int. Conf. VLSI Design, Bangalore, India, Jan. 2002, pp. 661-667.