System-level design hardening based on worst-case ASET simulations

IEEE Transactions on Nuclear Science

Volumn 51, Issue 5 III, 2004, Pages 2787-2793

  Boulghassoul, Y ^a   Adell, P C ^a   Rowe, J D ^a   Massengill, L W ^a   Schrimpf, R D ^a   Sternberg, A L ^a  

^a VANDERBILT UNIVERSITY   (United States)

Author keywords

Analog single event transients (ASETs); ASET propagation; LM124 and OP27 operational amplifiers; System level hardening by design

Indexed keywords

AMPLIFIERS (ELECTRONIC); COMPUTER SIMULATION; ELECTRIC POTENTIAL; HEAVY IONS; INTEGRATED CIRCUITS; SATELLITE COMMUNICATION SYSTEMS; TRANSISTORS;

ANALOG SINGLE-EVENT TRANSIENTS (ASET); ASET PROPAGATION; LM124 AND OP27 OPERATIONAL AMPLIFIERS; SYSTEM-LEVEL HARDENING BY DESIGN;

SYSTEMS ANALYSIS;

EID: 8344219880     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.835091     Document Type: Article

References (8)

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