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Volumn 54, Issue 10, 2011, Pages 12-17

The era of fully-depleted devices

Author keywords

[No Author keywords available]

Indexed keywords

BULK TECHNOLOGIES; FULLY DEPLETED; FULLY DEPLETED DEVICES; GATE ELECTRODES; IC INDUSTRY; POWER REQUIREMENT; SILICON ON INSULATOR; ULTRA-THIN; UNDOPED CHANNELS;

EID: 82755171141     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article
Times cited : (6)

References (17)
  • 2
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    • Fully-depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-Si-loss and faced raised S/D
    • K. Cheng et al, "Fully-depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-Si-loss and faced raised S/D," VLSI Symp., pp 212-213 (2009).
    • (2009) VLSI Symp. , pp. 212-213
    • Cheng, K.1
  • 3
    • 77954214538 scopus 로고    scopus 로고
    • Benchmarking SOI and Bulk FinFET alternative for planar CMOS scaling succession
    • T. Chiarella et al, "Benchmarking SOI and Bulk FinFET alternative for planar CMOS scaling succession," Solid-state Electronics 54, pp 855-860, (2010).
    • (2010) Solid-state Electronics , vol.54 , pp. 855-860
    • Chiarella, T.1
  • 4
    • 79960888821 scopus 로고    scopus 로고
    • W. Schwarzenbach et al, ECS Trans, vol. 35, No. 5, pp 239-245, (2011).
    • (2011) ECS Trans , vol.35 , Issue.5 , pp. 239-245
    • Schwarzenbach, W.1
  • 5
    • 1442360367 scopus 로고    scopus 로고
    • SmartCut technology: From 300mm ultrathin SOI production to advanced engineered substrates
    • C. Maleville et al, "SmartCut technology: from 300mm ultrathin SOI production to advanced engineered substrates," Solid-state Electron. 48 (6), pp. 1055-1063 (2004).
    • (2004) Solid-state Electron. , vol.48 , Issue.6 , pp. 1055-1063
    • Maleville, C.1
  • 6
    • 71049181314 scopus 로고    scopus 로고
    • High immunity to threshold voltage variation in undoped ultra-thin FDSOI MOSFETs and its physical understanding
    • # 10.4
    • O. Weber et al, "High immunity to threshold voltage variation in undoped ultra-thin FDSOI MOSFETs and its physical understanding," IEDM Tech. Digest, # 10.4 (2008).
    • (2008) IEDM Tech. Digest
    • Weber, O.1
  • 7
    • 79951828291 scopus 로고    scopus 로고
    • Planar fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
    • paper 3.2.3
    • O. Faynot et al, "Planar fully depleted SOI technology: a powerful architecture for the 20nm node and beyond," IEDM Tech. Digest, paper 3.2.3 (2010).
    • (2010) IEDM Tech. Digest
    • Faynot, O.1
  • 8
    • 79960860285 scopus 로고    scopus 로고
    • III-V/Ge CMOS on Si Platform
    • S. Takagi et al, "III-V/Ge CMOS on si Platform," VLSI Symposium, pp. 147-148, (2010).
    • (2010) VLSI Symposium , pp. 147-148
    • Takagi, S.1
  • 9
    • 1442360362 scopus 로고    scopus 로고
    • Multiple gate SOI MOSFETs
    • J.-P. Colinge, "Multiple gate SOI MOSFETs," Solid-state Electron. 48 (6), pp. 897-905 (2004).
    • (2004) Solid-state Electron. , vol.48 , Issue.6 , pp. 897-905
    • Colinge, J.-P.1
  • 10
    • 0038546631 scopus 로고    scopus 로고
    • Ultimately thin double-gate SOI MOSFETs
    • Mar.
    • T. Ernst et a l , "Ultimately thin double-gate SOI MOSFETs," IEEE Trans. On ED, Vol. 50, No 3, pp 830-838, (Mar. 2003).
    • (2003) IEEE Trans. On ED, Vol. , vol.50 , Issue.3 , pp. 830-838
    • Ernst, T.1
  • 12
    • 46049091193 scopus 로고    scopus 로고
    • Performances and variability comparisons between multi-gate FETs and planar SOI transistors
    • paper 34.2
    • A. Thean et al, "Performances and variability comparisons between multi-gate FETs and planar SOI transistors," IEDM Tech. Digest, paper 34.2 (2006).
    • (2006) IEDM Tech. Digest
    • Thean, A.1
  • 13
    • 79960842933 scopus 로고    scopus 로고
    • Work Function engineering in gate-first technology for multi-Vt dual gate FDSOI CMOS on UTBOX
    • # 27.5
    • O. Webber et al, "Work Function engineering in gate-first technology for multi-Vt dual gate FDSOI CMOS on UTBOX," IEDM Tech. Digest, # 27.5 (2010).
    • (2010) IEDM Tech. Digest
    • Webber, O.1
  • 14
    • 80052680200 scopus 로고    scopus 로고
    • Impact of back-bias on ultra-thin body and BOX (UTBB) Devices
    • Q. Liu et al, "Impact of back-bias on ultra-thin body and BOX (UTBB) Devices," VLSI Symposium, pp 16-161, (2011).
    • (2011) VLSI Symposium , pp. 16-161
    • Liu, Q.1
  • 15
    • 82755184297 scopus 로고    scopus 로고
    • FDSOI design migration from bulk at 20nm node
    • Taiwan, (Apr.2011)
    • J.L. Pelloie, "FDSOI design migration from bulk at 20nm node," FDSOI Workshop, Taiwan, (Apr.2011) (http://www.soiconsortium.org/corners/fully- depleted-soi/april-2011).
    • FDSOI Workshop
    • Pelloie, J.L.1
  • 16
    • 82755190121 scopus 로고    scopus 로고
    • Low power and high speed at low voltage for mobile applications
    • San Francisco, (Dec 2010)
    • T. Skotnicki, "Low power and high speed at low voltage for mobile applications," FDSOI Workshop, San Francisco, (Dec 2010) (http://www.soiconsortium.org/corners/fully-depletedsoi/ december-2010/index. php).
    • FDSOI Workshop
    • Skotnicki, T.1
  • 17
    • 82755184296 scopus 로고    scopus 로고
    • http://www.icknowledge.com/misc-technology/SoitecReport20ll0709.pdf


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.