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Volumn 8166, Issue , 2011, Pages

Exploring the impact of mask making constraints on double patterning design rules

Author keywords

Design rule development; ILT; Inverse Lithography; MRC; OPC; SMO; Source mask optimization

Indexed keywords

DESIGN RULES; ILT; INVERSE LITHOGRAPHY; MRC; OPC; SMO;

EID: 81455147487     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.896963     Document Type: Conference Paper
Times cited : (2)

References (10)
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    • Pyo, Y.-J., Choi, S.-H., Park, C.-H., Lee, S.-H., Yoo, M.-H., and Kim, G.-T., "Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device", Proc. of SPIE 797413, 797413-1-7 (2011).
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    • Double patterning for a 56-nm pitch metal layer test design using inverse lithography
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    • Rissman, P.1    Dam, T.2    Gleason, R.3    Sinn, R.4
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    • (2011) Proc. of SPIE , vol.8166
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.