Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

Journal of Micro/Nanolithography, MEMS, and MOEMS

Volumn 8, Issue 3, 2009, Pages

  Lucas, Kevin ^a   Miloslavsky, Alexander ^b   Luk Pat, Gerard ^a   Barnes, Levi ^a   Cork, Christopher ^a   Hapli, John ^a   Lewellen, John ^a   Rollins, Greg ^a   Wiaux, Vincent ^c   Verhaegen, Staf ^c  

^a SYNOPSYS INC   (United States)

^b Synopsys SARL   (France)

^c IMEC   (Belgium)

Author keywords

Design rules; Double patterning technology (DPT); Place route; Standard cell design

Indexed keywords

ELECTRIC BATTERIES; TITRATION;

193-NM LITHOGRAPHY; CRITICAL SOFTWARE; DESIGN FLOWS; DESIGN RULES; DOUBLE EXPOSURE; DOUBLE PATTERNING; DOUBLE-PATTERNING TECHNOLOGY (DPT); MASK SYNTHESIS; MASKING LAYERS; OPTICAL PROXIMITY CORRECTIONS; ORIGINAL DESIGN; PATTERNING LAYERS; PHYSICAL DESIGN; SINGLE EXPOSURE; STANDARD CELL DESIGN; WAFER PROCESSING;

DESIGN;

EID: 77953492760     PISSN: 19325150     EISSN: 19325134     Source Type: Journal    
DOI: 10.1117/1.3158061     Document Type: Conference Paper

References (3)

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