Litho/design co-optimization and area scaling for the 22-nm logic node

ECS Transactions

Volumn 27, Issue 1, 2010, Pages 449-454

  Blatchford, James W ^a   Prins, Steven L ^a   Jessen, Scott W ^a   Dam, Thuc ^b   Baik, KiHo ^b   Pang, Linyong ^b   Gleason, Bob ^b  

^a TEXAS INSTRUMENTS   (United States)

^b Luminescent Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MASKS; SEMICONDUCTOR DEVICE MANUFACTURE;

ADDITIONAL COSTS; AREA SCALING; CO-OPTIMIZATION; DESIGN RULES; DOUBLE PATTERNING; METAL LAYER; SINGLE EXPOSURE; SOURCE-MASK OPTIMIZATIONS;

COMPUTER CIRCUITS;

EID: 84857409852     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3360658     Document Type: Conference Paper

References (7)

1. See, for example, L. Pang et al., Photomask Technology Proc. 7122 (2008).
2. A. Engelen et al., Proc. SPIE 7274, 72741K (2009).
3. J. Finders et al., Proc. SPIE 6924, 692408 (2008).
4. See, for example, G. Zhang et al., Proc. SPIE 5754, 760 (2005).
5. V. Wiaux et al., Proc. SPIE 6924, 692409 (2008).
6. V. Wiaux, presented at the 2009 Immersion Lithography Symposium, Prague CZ.
7. S. Chang et al., Proc. SPIE 7275, 72750D (2009).