Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7974, Issue , 2011, Pages

  Pyo, Yu Jin ^a   Choi, Soo Han ^a,b   Park, Chul Hong ^a   Lee, Sang Hoon ^a   Yoo, Moon Hyun ^a   Kim, Gyu Tae ^b  

^a SAMSUNG Electronics   (South Korea)

^b Korea University   (South Korea)

Author keywords

Double patterning; DRAM; Electrical performance; Hotspot; Process specification

Indexed keywords

DOUBLE PATTERNING; DRAM; ELECTRICAL PERFORMANCE; HOT SPOT; PROCESS SPECIFICATION;

DEGRADATION; LITHOGRAPHY; MACHINE DESIGN; SPECIFICATIONS;

TITRATION;

EID: 79955874018     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.869978     Document Type: Conference Paper

References (6)

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6. A. B. Kahng, C. H. Park, X. Xu, and H. Yao, "Layout Decomposition for Double Patterning Lithography", Proc. ICCAD, pp. 465-472 (2008)