Generation of distributed logic-memory architectures through high-level synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 11, 2005, Pages 1694-1710

  Huang, Chao ^a,b   Ravi, Srivaths ^a,c   Raghunathan, Anand ^a,c   Jha, Niraj K ^a,b,d  

^a IEEE

^b Princeton University   (United States)

^c NEC LABORATORIES AMERICA   (United States)

^d New Jersey Commission on Science and Technology   (United States)

Author keywords

Distributed architectures; High level synthesis; Logic memory architectures; Scheduling

Indexed keywords

DISTRIBUTED ARCHITECTURES; HIGH-LEVEL SYNTHESIS; LOGIC-MEMORY ARCHITECTURES; MONOLITHIC CONTROLLER;

COMMUNICATION SYSTEMS; COMPUTATION THEORY; COMPUTER HARDWARE; FORMAL LOGIC; MICROPROCESSOR CHIPS; SCHEDULING; SYNCHRONIZATION;

COMPUTER ARCHITECTURE;

EID: 27744551146     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.852276     Document Type: Article

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