MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 1352-1357

  Lange, Holger ^a   Wink, Thorsten ^a   Koch, Andreas ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH PREDICTION; DEDICATED HARDWARE; HARDWARE COMPILERS; MAIN MEMORY; MEMORY OPERATORS; MEMORY PORTS; MEMORY SUBSYSTEMS; MEMORY SYSTEMS; PARAMETERIZED; RECONFIGURABLE COMPUTER; SHARED RESOURCES; SPATIAL COMPUTATIONS; SPECULATIVE EXECUTION;

HIGH LEVEL LANGUAGES; RECONFIGURABLE HARDWARE;

COMPUTER HARDWARE;

EID: 79957551380     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)

1. AMD Inc., "AMD64 Architecture Programmer's Manual Vol 2: System Programming", 2007.
2. Batcher K. E., "Sorting networks and their applications", AFIPS Conf. Proc. 32, 1968.
3. Bobba J., Goyal N., Hill M. D., Swift M. M., Wood D. A., "TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory", Proc. 35th Intl. Symp. on Comp. Arch., 2008
4. Ebrahimi E., et al., "Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems", Proc. Intl. Symp. on High-Perf. Comp. Arch., 2009
5. EEMBC, "What is CoreMark?", www.coremark.org, 2009
6. Gädke, H., Stock, F., Koch, A., "Memory Access Parallelization in High- Level Language Compilation for Reconfigurable Adaptive Computers", Proc. Intl. Conf. on Field Programmable Logic, 2008
7. Gädke-Lütjens, H., Thielmann, B., Koch, A., "A Flexible Compute and Memory Infrastructure for High-Language to Hardware Compilation", Proc. Intl. Conf. on Field-Programmable Logic, 2010.
8. Hennessy, J.L., Patterson, D.A., "Computer Architecture: A Quantitative Approach", Morgan Kaufmann, 2006
9. Hind, M., Pioli, A., "Which pointer analysis should I use?", Proc. Intl. Symp. on SW Testing and Analysis, 2000
10. Hung, A. et al., "Symmetric Multiprocessing on Programmable Chips Made Easy", Proc. DATE, 2005
11. Intel Corp, "Intel 64 and IA-32 Architectures Optimization Reference Manual", March 2009.
12. Intel Corp., "First the Tick, Now the Tock: Intel Microarchitecture (Nehalem)", White Paper No. 319724, 2009.
13. Kaeli D. R., Yew P.-C., "Speculative execution in high-performance computer architectures", Chapman & Hall/CRC, 2005.
14. Koch, A., "Advances in Adaptive Computer Technology", habilitation thesis, TU Braunschweig (Germany), 2004
15. Lange, H., Koch, A., "Memory Access Schemes for Configurable Processors", Proc. Intl. Conf. on Field-Programmable Logic, 2000
16. Lange H., Koch A., "Architectures and Execution Models for Hardware/- Software Compilation and their System-Level Realization", IEEE Trans. on Computers, IEEE Digital Lib., 12-2009.
17. Marcuello P., Gonzalez A., Tubella J., "Speculative multithreaded processors", Proc. 12th Intl. Conf. on Supercomputing,1998
18. Martynus M., "Branch Predictor Simulator", Bachelor Thesis, TU Darmstadt (Germany), 2007.
19. Putnam, A., et al., "CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures", Proc. Intl. Conf. on Field-Programmable Logic, 2008
20. Sendag, R., et al., "Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions", Proc. Euro-Par Conf., 2002
21. Shen J. P., Lipasti M., "Modern Processor Design", McGraw-Hill, 2005.
22. SPEC CPU Subcommittee, original program authors, "SPEC CPU2006 Benchmark Descriptions", SPEC - Standard Performance Evaluation Corp., 2006
23. Woods, D. "Coherent Shared Memories for FPGAs", Master Thesis, U Toronto, 2009
24. XILINX Inc, "LogiCORE IP DDR2 Memory Controller for PowerPC 440", 2010
25. XILINX Inc, "ML505/ML506/ML507 Reference Design User Guide", UG 349, 2009
26. Yeh T. Y., Patt Y. N., "Alternative Implementations of Two-Level Adaptive Branch Prediction", Proc. 19th Intl. Symp. on Comp. Arch. (ISCA), 1992.