BISS: A built-in SEU sensor for soft error mitigation

Applied Mechanics and Materials

Volumn 130-134, Issue , 2012, Pages 4228-4231

  Huang, Zhengfeng ^a   Yi, Maoxiang ^a  

^a HEFEI UNIVERSITY OF TECHNOLOGY   (China)

Author keywords

Built in SEU sensor; Meta stability; Single event upset; Soft errors

Indexed keywords

AREA OVERHEAD; DIGITAL SYSTEM; DYNAMIC INVERTERS; ERROR COVERAGE; META-STABILITY; PERFORMANCE DEGRADATION; SINGLE EVENT UPSETS; SOFT ERROR; SPICE SIMULATIONS;

ELECTRONICS ENGINEERING; ERROR CORRECTION; PULSE GENERATORS; SENSORS;

MICROPROCESSOR CHIPS;

EID: 81255125336     PISSN: 16609336     EISSN: 16627482     Source Type: Book Series    
DOI: 10.4028/www.scientific.net/AMM.130-134.4228     Document Type: Conference Paper

References (12)

1. Zhengfeng Huang, Huaguo Liang, "A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies," Proc. IEEE Int'l On-Line Testing Symp., 2008, pp.175-176
2. Q.Zhou, K.Mohanram, "Gate Sizing to Radiation Harden Combinational logic", IEEE Trans. CAD, vol.25, no.1, 2006,pp.155-166
3. S.Mitra, N.Seifert, M.Zhang, et al, "Robust System Design with Built-In Soft-Error Resilience ," IEEE Trans. Computer, vol.38, no.2, Feb.2005, pp.43-52
4. K.Reick, P.N.Sanda, S.Swaney, et al, "Fault-tolerant Design of the IBM Power6 Microprocessor," IEEE Tran. Micro, vol.28, no.2, 2008, pp.30-38
5. S.S.Mukherjee,M.Kontz,S.K.Reinhardt,"Detailed Design and Evaluation of Redundant Multi- Threading Alternatives," Proc. Intl.Symp. Computer Architecture, 2002, pp.99-110
6. Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, "A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery ," Proc. IEEE/IFIP Int'l Conf. Dependable Systems and Networks, 2007,pp.256-265
7. M. Nicolaidis, " Design for soft error mitigation," IEEE Trans.Device and Materials Reliability, vol.5,no.3, 2005, pp.405-418
8. N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Addison Wesley, 2004.
9. E. L. Hill, M. H. Lipasti, and K. K. Saluja, "An accurate flip-flop selection technique for reducing logic SER," Proc.Int'l Conf. Dependable Systems and Networks, 2008:128-136
10. http://www.eas.asu.edu/~ptm/
11. G. C. Messenger, "Collection of Charge on Junction Nodes from Ion Tracks,"IEEE Trans. Nuclear Science, vol.29,no.6,1982, pp.2024-2031
12. D. Bull, S. Das, K.Shivashankar, et al, "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation," IEEE Journal of Solid State Circuits, vol.46,no.1,2011, pp.18-31