High efficiency architecture design of real-time QFHD for H.264/AVC fast block motion estimation

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 21, Issue 11, 2011, Pages 1646-1658

  Tsai, Tsung Han ^a   Pan, Yu Nan ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

Fast block matching algorithm; H264; high efficiency architecture; motion estimation; QFHD

Indexed keywords

ANALYTICAL RESULTS; ARCHITECTURE DESIGNS; BLOCK MOTION ESTIMATION; BLOCK SIZES; CODING GAINS; EDGE INFORMATION; EDGE INFORMATION MODE DECISION; FAST BLOCK MATCHING ALGORITHMS; FIXED BLOCK; GATE COUNT; GENERAL SPECIFICATION; H.264/AVC; H264; HIGH DEFINITION; HIGH EFFICIENCY; MACRO BLOCK; MEMORY USAGE; MOTION VECTORS; MPEG-4 AVC; OPERATING FREQUENCY; OPERATION FREQUENCY; PEAK SIGNAL-TO-NOISE RATIO; PROPOSED ARCHITECTURES; QFHD; RATE DISTORTION PERFORMANCE; REAL TIME EXECUTION; REFERENCE FRAME; SEARCH RANGE; STANDARD DEFINITIONS; VIDEO CODING STANDARD;

ALGORITHMS; ESTIMATION; IMAGE CODING; MEMORY ARCHITECTURE; MOTION PICTURE EXPERTS GROUP STANDARDS; SIGNAL TO NOISE RATIO; SPECIFICATIONS;

MOTION ESTIMATION;

EID: 80455149716     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2011.2133230     Document Type: Article

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