High frequency trading acceleration using FPGAs

Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011

Volumn , Issue , 2011, Pages 317-322

  Leber, Christian ^a   Geib, Benjamin ^a   Litz, Heiner ^a  

^a UNIVERSITY OF HEIDELBERG   (Germany)

Author keywords

Ethernet; FAST; FIX; FPGA; High frequency trading; Low latency; UDP

Indexed keywords

FAST; FIX; HIGH FREQUENCY; LOW LATENCY; UDP;

ELECTRONIC DATA INTERCHANGE; ETHERNET; ETHERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERNET PROTOCOLS;

COMMERCE;

EID: 80455132109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2011.64     Document Type: Conference Paper

References (18)

1. J.A. Brogaard, "High Frequency Trading and its Impact on Market Quality," 5th Annual Conference on Empirical Legal Studies, 2010.
2. M. Chlistalla, "High-frequency trading Better than its reputation?," Deutsche Bank research report, 2011.
3. A. Group, New World Order: The High Frequency Trading Community and Its Impact on Market Structure, 2009.
4. K.H. Chung and Y. Kim, "Volatility, Market Structure, and the Bid-Ask Spread," Asia-Pacific Journal of Financial Studies, vol. 38, Feb. 2009.
5. J. Chiu, D. Lukman, K. Modarresi, and A. Velayutham, "Highfrequency trading," Stanford University Research Report, 2011.
6. H. Subramoni, F. Petrini, V. Agarwal, and D. Pasetto, "Streaming, lowlatency communication in on-line trading systems," International Symposium on Parallel & Distributed Processing, Workshops (IPDPSW), 2010.
7. V. Agarwal, D. a Bader, L. Dan, L.-K. Liu, D. Pasetto, M. Perrone, and F. Petrini, "Faster FAST: multicore acceleration of streaming financial data," Computer Science - Research and Development, vol. 23, May. 2009.
8. G.W. Morris, D.B. Thomas, and W. Luk, "FPGA Accelerated Low-Latency Market Data Feed Processing," 2009 17th IEEE Symposium on High Performance Interconnects, Aug. 2009.
9. F. Herrmann and G. Perin, "An UDP/IP Network Stack in FPGA," Electronics, Circuits, and Systems (ICECS), 2009.
10. G.L. Zhang, P.H.W. Leong, C.H. Ho, K.H. Tsoi, C.C.C. Cheung, D. Lee, R.C.C. Cheung, and W. Luk, "Reconfigurable acceleration for Monte Carlo based financial simulation," IEEE International Conference on Field-Programmable Technology, 2005.
11. D.B. Thomas, "Acceleration of Financial Monte-Carlo Simulations using FPGAs," Workshop on High Performance Computational Finance (WHPCF), 2010.
12. N. a Woods and T. VanCourt, "FPGA acceleration of quasi-Monte Carlo in finance," 2008 International Conference on Field Programmable Logic and Applications, 2008, pp. 335-340.
13. M. Sadoghi, M. Labrecque, H. Singh, W. Shum, and H.-arno Jacobsen, "Efficient Event Processing through Reconfigurable Hardware for Algorithmic Trading," Journal Proceedings of the VLDB Endowment, 2010.
14. S. Tandon, "A Programmable Architecture for Real-time Derivative Trading," Master Thesis, University of Edinburgh, 2003.
15. S. Larsen and P. Sarangam, "Architectural Breakdown of End-to-End Latency in a TCP/IP Network," International Journal of Parallel Programming, Springer, 2009.
16. D. Slogsnat, A. Giese, M. Nüssle, and U. Brüning, "An open-source HyperTransport core," ACM Transactions on Reconfigurable Technology and Systems, vol. 1, Sep. 2008, pp. 1-21.
17. G. Mittal, D.C Zaretsky, P. Banerjee, "Streaming implementation of a sequential decompression algorithm on an FPGA," International Symposium on Field Programmable Gate Arrays - FPGA09, 2009.
18. FIX adapted for Streaming, www.fixprotocol.org/fast