FPGA accelerated low-latency market data feed processing

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects

Volumn , Issue , 2009, Pages 83-89

  Morris, Gareth W ^a   Thomas, David B ^b   Luk, Wayne ^b  

^a Celoxica Inc   (United States)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CELOXICA; COMPLETE SYSTEM; DATA FEED; DATA RATES; GENERAL PURPOSE PROCESSORS; GIGABIT ETHERNET; HIGH THROUGHPUT; LOW LATENCY; MARKET DATA; MARKET PLACE; NETWORK STACK; OPERATING SYSTEMS; REAL-WORLD; REDUNDANT DATA; SYSTEM MEMORY;

COMMERCE; COMPUTER OPERATING SYSTEMS; ELECTRONIC DATA INTERCHANGE; ETHERNET; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); WIRELESS SENSOR NETWORKS;

DATA PROCESSING;

EID: 77950955284     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HOTI.2009.17     Document Type: Conference Paper

References (7)

1. T. J. Todman, G. A. Constantinides, S. J. E. Wilton, O. Mencer, W. Luk, and P. Y. K. Cheung, "Reconfigurable computing: architectures and design methods," IEE Proc. Computing and Digital Techniques, vol.152, no.2, pp. 193-207, 2004.
2. K. Houstoun, FIX Adapted for STreaming - FAST Protocol Technical Overview, 2006.
3. Handel-C Language Reference, http://www.celoxica.com, Celoxica Ltd., 1999.
4. G. W. Morris and M. Aubury, "Design space exploration of the European option benchmark using Hyperstreams," in FPL, 2007, pp. 5-10.
5. S. T. A. Center, "Exegy ticker plant with infiniband," STAC Report, July 2007.
6. "Activefeed MPU: Accelerate your market data," http://www.activfinancial.com/docs/ActivFeedMPU.pdf, 2007.
7. K. C, G. Brebner, and G. Schelle, "Mapping a domain specific language to a platform FPGA," in Proc. IEEE Design Automation Conference, 2004, pp. 924-927.