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Volumn 46, Issue 11, 2011, Pages 2535-2544

A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

Author keywords

28 nm; 8T; CMOS; disturb; dual port; embedded SRAM; memory; screening; testability

Indexed keywords

28 NM; 8T; CMOS; DISTURB; DUAL PORT; EMBEDDED SRAM; MEMORY; TESTABILITY;

EID: 80255136213     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2164021     Document Type: Conference Paper
Times cited : (26)

References (6)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.