A 65 nm single-chip application and dual-mode baseband processor with partial clock activation and IP-MMU

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 83-89

  Ito, Masayuki ^a   Nitta, Kenichi ^a   Ohno, Koji ^b   Saigusa, Masahito ^b   Nishida, Masaki ^c   Yoshioka, Shinichi ^a   Irita, Takahiro ^a   Koike, Takao ^a   Kamei, Tatsuya ^a   Komuro, Teruyoshi ^d   Hattori, Toshihiro ^a   Arai, Yasuhiro ^e   Kodama, Yukio ^f  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NTT DOCOMO   (Japan)

^c SHARP CORPORATION   (Japan)

^d SONY CORPORATION   (Japan)

^e FUJITSU LABORATORIES LTD   (Japan)

^f MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Application processor; Baseband processor; Cellular phone; Clock activation; Memory space; Power domains

Indexed keywords

APPLICATIONS; DECODING; INTERNET PROTOCOLS; MOBILE PHONES; PROGRAM TRANSLATORS; TELEPHONE SETS;

APPLICATION PROCESSOR; BASEBAND PROCESSOR; CELLULAR PHONE; MEMORY SPACE; POWER DOMAINS;

CLOCKS;

EID: 58149214107     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007169     Document Type: Conference Paper

References (5)

1. T. Hattori et al., "A power management scheme controlling 20 power domains for a single-chip mobile processor," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 542-543.
2. M. Ito et al., "A 390 MHz single-chip application and dual-mode baseband processor in 90 nm triple-Vth CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 274-275.
3. G. Gammie et al., "A 45 nm 3.5 G baseband-and-multimedia application processor using adaptive body-bias and ultra-low-power techniques," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 258-259.
4. T. Kamei et al., "A resume-standby application processor for 3 G cellular phones," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 336-337.
5. Y. Kanno et al., "Hierarchical power distribution with power-tree in dozens power domains for 90-nm low-power multi-CPU SoCs," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 74-83, Jan. 2007.