A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 99-100

  Ishii, Y ^a   Fujiwara, H ^a   Nii, K ^a   Chigasaki, H ^b   Kuromiya, O ^c   Saiki, T ^c   Miyanishi, A ^a   Kihara, Y ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Northern Japan Semiconductor Inc   (Japan)

^c Renesas Design Corporation   (Japan)

Author keywords

28 nm; 8T; Dual port; SRAM; Write disturb

Indexed keywords

28-NM; 8T; DUAL PORT; SRAM; WRITE DISTURB;

CMOS INTEGRATED CIRCUITS; VLSI CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 77957996635     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560339     Document Type: Conference Paper

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