Decentralized dynamic resource management support for massively parallel processor arrays

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2011, Pages 87-94

  Lari, Vahid ^a   Narovlyanskyy, Andriy ^a   Hannig, Frank ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION REQUIREMENTS; CENTRALIZED RESOURCES; DISTRIBUTED APPROACHES; DISTRIBUTED RESOURCES; DYNAMIC RESOURCE MANAGEMENT; EXPLORATION METHODS; EXPLORATION STRATEGIES; HARDWARE COST; MASSIVELY PARALLEL PROCESSORS; PARALLEL PROGRAM; PRO-GRAMMABLE CONTROLLERS; PROCESSING ELEMENTS; RESOURCE AVAILABILITY; RESOURCE MANAGEMENT;

ARCHITECTURE; COMPUTER ARCHITECTURE; CONTROLLERS; NATURAL RESOURCES EXPLORATION; NATURAL RESOURCES MANAGEMENT; PARALLEL ARCHITECTURES; PROCESS CONTROL; PROGRAMMABLE LOGIC CONTROLLERS; RESOURCE ALLOCATION;

PARALLEL PROCESSING SYSTEMS;

EID: 80055098058     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2011.6043240     Document Type: Conference Paper

References (16)

1. K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S. Keckler, and D. Burger, "Distributed microarchitectural protocols in the TRIPS prototype processor," in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Orlando, Florida, USA, Dec. 2006, pp. 480-491.
2. P. Palatin, Y. Lhuillier, and O. Temam, "CAPSULE: Hardware-assisted parallel execution of component-based programs," in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Orlando, Florida, USA, Dec. 2006, pp. 247-258.
3. O. Certner, Z. Li, P. Palatin, O. Temam, F. Arzel, and N. Drach, "A practical approach for reconciling high and predictable performance in non-regular parallel programs," in Proceedings of Design, Automation and Test in Europe (DATE), Munich, Germany, Mar. 2008, pp. 740-745.
4. F. Thoma, M. Kühnle, P. Bonnot, E. Panainte, K. Bertels, S. Goller, A. Schneider, S. Guyetant, E. Schüller, K. Müller-Glaser, and J. Becker, "MORPHEUS: Heterogeneous reconfigurable computing," in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, Netherlands, Aug. 2007, pp. 409-414.
5. J. Resano, D. Mozos, and F. Catthoor, "A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware," in Proceedings of Design, Automation and Test in Europe (DATE), vol. 1, Munich, Germany, Mar. 2005, pp. 106-111.
6. R. Maestre, M. Fernandez, F. Kurdahi, N. Bagherzadeh, and H. Singh, "Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations," in Proceedings of the International Symposium on System Synthesis (ISSS), Madrid, Spain, Sep. 2000, pp. 106-111.
7. L. Shang and N. Jha, "Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs," in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Bangalore, India, Jan. 2002, pp. 345-360.
8. M. Motomura, "A dynamically reconfigurable processor architecture," in Microprocessor Forum, San Jose, CA, USA, Oct. 2002.
9. V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt, "PACT XPP - a self-reconfigurable data processing architecture," The Journal of Supercomputing, vol. 26, pp. 167-184, 2003.
10. F. Bouwens, M. Berekovic, B. De Sutter, and G. Gaydadjiev, "Architecture enhancements for the ADRES coarse-grained reconfigurable array," in Proceedings of the 3rd International Conference on High Performance Embedded Architectures and Compilers (HiPEAC). Gothenburg, Sweden: Springer, 2008, pp. 66-81.
11. Y. Yi, W. Han, X. Zhao, A. T. Erdogan, and T. Arslan, "An ILP formulation for task mapping and scheduling on multi-core architectures," in Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE), Nice, France, Apr. 2009, pp. 33-38.
12. G. Sun, Y. Li, Y. Zhang, L. Su, D. Jin, and L. Zeng, "Energy-aware run-time mapping for homogeneous NoC," in Proceedings of the International Symposium on System on Chip (SoC), Tampere, Finland, Sep. 2010, pp. 8-11.
13. D. Kissler, F. Hannig, A. Kupriyanov, and J. Teich, "A highly parameterizable parallel processor array architecture," in Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), Bangkok, Thailand, Dec. 2006, pp. 105-112.
14. F. Arifin, R. Membarth, A. Amouri, F. Hannig, and J. Teich, "FSM-controlled architectures for linear invasion," in Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Florianópolis, Brazil, Oct. 2009.
15. V. Lari, F. Hannig, and J. Teich, "Distributed resource reservation in massively parallel processor arrays," International Symposium on Parallel and Distributed Processing Symposium (IPDPS), May 2011.
16. S. S. Beauchemin and J. L. Barron, "The computation of optical flow," ACM Comput. Surv., vol. 27, pp. 433-466, Sep. 1995. [Online]. Available: http://doi.acm.org/10.1145/212094.212141