A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 388-389

  Harpe, Pieter ^a   Zhou, Cui ^a   Wang, Xiaoyan ^a   Dolmans, Guido ^a   De Groot, Harmke ^a  

^a HOLST CENTRE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; LOW POWER APPLICATION; LOW POWER RECEIVER; POWER EFFICIENT; POWER-EFFICIENCY; SAMPLING RATES; SAR ADC; SYSTEM LEVELS; WIRELESS SENSOR NODE;

ELECTRIC NETWORK SYNTHESIS; SENSOR NODES;

TELECOMMUNICATION EQUIPMENT;

EID: 77952194722     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433967     Document Type: Conference Paper

References (4)

1. M. van Elzakker, et al., "A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC," ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2008.
2. V. Giannini, et al., "An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008.
3. J. McCreary, P. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques - Part I," IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
4. J.M. Rabaey, Digital Integrated Circuits - A Design Perspective, Prentice-Hall International, 1996.