A study of inverse narrow width effect of 65nm low power CMOS technology

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 1138-1141

  Xinfu, Liu ^a   Kheeyong, Lim ^a   Zhihua, Wu ^a   Zhibin, Xiong ^a   Yongping, Ding ^a   Hao, Nong ^a   Yanping, Wu ^a   Yanping, Shen ^a   Bin, Tang ^a   Louis, Lim ^a   Sally, Chwa ^a   Xing, Yu ^a   Feng, Hong ^a   Yang, Simon ^a  

^a CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL GATE OXIDES; GATE OXIDATIONS; INVERSE NARROW WIDTH EFFECTS; LOW POWER CMOS; LOW-POWER; MOSFETS; NARROW WIDTHS; PROCESS STEPS;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; NITRIDES; OXIDATION; SPEECH ANALYSIS;

SEMICONDUCTING SILICON;

EID: 60649103138     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734750     Document Type: Conference Paper

References (3)

1. Stanley Wolf, Silicon Processing for the VLSI Era, Vol 3, P221
2. J. Kim, T. Kim, et al., "A shallow trench isolation using nitric oxide (NO)-annealed wall oxide to suppress inverse narrow-width effect, "IEEE Electron Device Lett., Vol. 21, pp.575-577,(Dec 2000).
3. Hyeokjae Lee, et al., An Anomalous Device Degradation of SOI Narrow Width Devices Caused by STI Edge Influence, IEEE Transactions on Electron devices. Vol.49, pp605-611 (April 2002)