Efficient architectures through application clustering and architectural heterogeneity

CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Volumn , Issue , 2006, Pages 190-200

  Strozek, Lukasz ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

Efficient custom architectures; Heterogeneous CMP

Indexed keywords

ARCHITECTURAL CUSTOMIZATION; EFFICIENT CUSTOM ARCHITECTURES; SENSOR NODE;

BENCHMARKING; CLUSTER ANALYSIS; EMBEDDED SYSTEMS; ENERGY CONSERVATION; MULTIMEDIA SYSTEMS; OPTIMIZATION;

COMPUTER ARCHITECTURE;

EID: 34547205574     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176760.1176784     Document Type: Conference Paper

References (18)

1. ARM Corporation. Thumb ISA http://www.arm.com/products/CPUs/ ARM7TDMI.html
2. J. Babb et al. The RAW Benchmark Suite: Computation Structures for General Purpose Computing. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Apr 1997.
3. Cadence Inc. SoC Encounter. http://www.cadence.com/products/digital_ic/ soc_encounter/
4. N. Clark, W. Tang and S. Mahlke. Automatically Generating Custom Instruction Set Extensions. First Annual Workshop on Application-Specific Processors, 2002, pp. 94-101.
5. J. A. Fisher, P. Faraboschi and G. Desoli. Custom-fit processors: Letting applications define architectures. In Proceedings of Microarchitecture, Dec. 2-4, 1996, pp. 324-335.
6. J. A. Fisher, F. Homewood, G. Brown, G. Desoli and P. Faraboschi. Lx: A Technology Platform for Customizable VLIW Embedded Processing. In Proceedings of International Symposium on Computer Architecture, 2000, p. 203.
7. C-L. Fok, G.-C. Roman and C. Lu. Mobile agent middleware for sensor networks: an application case study. In Proceedings of International Conference on Information Processing in Sensor Networks, Apr 2005.
8. M. R. Guthaus et al. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the Fourth IEEE Workshop Workload Characterization, pp. 10-12, Dec 2001.
9. J. L. Hill. System architecture for wireless sensor networks. PhD thesis, University of California, Berkeley, 2003.
10. A. Krishnaswamy, R. Gupta. Mixed-width instruction sets. In Communications of the ACM, Vol. 46, No. 8, 2003.
11. R. Kumar et al. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In 36th International Symposium on Microarchitecture, MICRO-36, Dec 2003.
12. L. Nazhandali, B. Zhai, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, T. Austin and D. Blaauw. Energy Optimization of Subthreshold-Voltage Sensor Network Processors. In Proceedings of International Symposium on Computer Architecture, 2005.
13. M. Poletto and V. Sarkar. Linear Scan Register Allocation. In ACM Transactions on Programming Languages and Systems, Vol. 21, No. 5, Sep 1999, pp. 895-913.
14. Standard Performance Evaluation Corporation. The Integer SPEC95 Benchmarks. http://www.spec.org/cpu95/CINT95/
15. Tensilica. Xtensa LX Processor. http://www.tensilica.com/products/ xtensa_LX.htm
16. Texas Instruments. TI MSP430 Product Brochure. http://focus.ti.com/lit/ml/slab034k/slab034k.pdf
17. UMC Faraday 0.13μm Libraries. http://freelibrary.faraday-tech.com/ips/ 013library.html.
18. G. Werner-Allen, J. Johnson, M. Ruiz, J. Lees and M. Welsh. Monitoring volcanic eruptions with a wireless sensor network. In Proceedings of European Workshop on Sensor Networks, Jan 2005.