-
1
-
-
70449575202
-
Fast code generation for embedded processors with aliased heterogeneous registers
-
AHN, M., AND PAEK, Y. Fast code generation for embedded processors with aliased heterogeneous registers. Trans. on HiPEAC 2, 2 (2007), 40-59.
-
(2007)
Trans. on HiPEAC
, vol.2
, Issue.2
, pp. 40-59
-
-
Ahn, M.1
Paek, Y.2
-
2
-
-
84869345560
-
Removing communications in clustered microarchitectures through instruction replication
-
ALETÀ, A., CODINA, J. M., GONZÁLEZ, A., AND KAELI, D. Removing communications in clustered microarchitectures through instruction replication. ACM Trans. Archit. Code Optim. 1, 2 (2004), 127-151.
-
(2004)
ACM Trans. Archit. Code Optim.
, vol.1-2
, pp. 127-151
-
-
Aletà, A.1
Codina, J.M.2
González, A.3
Kaeli, D.4
-
4
-
-
67650066363
-
Architecture enhancements for the ADRES coarse-grained reconfigurable array
-
BOUWENS, F., BEREKOVIC, M., GAYDADJIEV, G., AND DE SUTTER, B. Architecture enhancements for the ADRES coarse-grained reconfigurable array. In Proc. of HiPEAC Conf. (2008).
-
(2008)
Proc. of HiPEAC Conf.
-
-
Bouwens, F.1
Berekovic, M.2
Gaydadjiev, G.3
De Sutter, B.4
-
5
-
-
0028429472
-
Improvements to graph coloring register allocation
-
BRIGGS, P., COOPER, K. D., AND TORCZON, L. Improvements to graph coloring register allocation. ACM Trans. Program. Lang. Syst. 16, 3 (1994), 428-455.
-
(1994)
ACM Trans. Program. Lang. Syst.
, vol.16
, Issue.3
, pp. 428-455
-
-
Briggs, P.1
Cooper, K.D.2
Torczon, L.3
-
6
-
-
84976675935
-
Register allocation via hierarchical graph coloring
-
CALLAHAN, D., AND KOBLENZ, B. Register allocation via hierarchical graph coloring. SIGPLAN Not. 26, 6 (1991), 192-203.
-
(1991)
SIGPLAN Not
, vol.26
, Issue.6
, pp. 192-203
-
-
Callahan, D.1
Koblenz, B.2
-
7
-
-
0000291844
-
Exact solution of large-scale, asymmetric traveling salesman problems
-
CARPANETO, G., DELL'AMICO, M., AND TOTH, P. Exact solution of large-scale, asymmetric traveling salesman problems. ACM Trans. Math. Softw. 21, 4 (1995), 394-409.
-
(1995)
ACM Trans. Math. Softw.
, vol.21
, Issue.4
, pp. 394-409
-
-
Carpaneto, G.1
Dell'amico, M.2
Toth, P.3
-
9
-
-
0019398205
-
Register allocation via coloring
-
CHAINTIN, G., AUSLANDER, M., CHANDRA, A. K., COCKE, J., HOPKINS, M., AND MARKSTEIN, P. Register allocation via coloring. Computer Languages 6, 1 (1981), 47-57.
-
(1981)
Computer Languages
, vol.6
, Issue.1
, pp. 47-57
-
-
Chaintin, G.1
Auslander, M.2
Chandra, A.K.3
Cocke, J.4
Hopkins, M.5
Markstein, P.6
-
10
-
-
0038039846
-
Region-based hierarchical operation partitioning for multicluster processors
-
CHU, M., FAN, K., AND MAHLKE, S. Region-based hierarchical operation partitioning for multicluster processors. In PLDI '03: Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation (2003), pp. 300-311.
-
(2003)
PLDI '03: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation
, pp. 300-311
-
-
Chu, M.1
Fan, K.2
Mahlke, S.3
-
11
-
-
84865698748
-
Circular-arc graph coloring and unrolling
-
Twente, Netherlands, May, U. Faigle and C. Hoede, Eds.
-
EISENBEIS, C., LELAIT, S., AND MARMOL, B. Circular-arc graph coloring and unrolling. In Proceedings of the 5th Twente Workshop on Graphs and Combinatorial Optimization (Twente, Netherlands, May 1997), U. Faigle and C. Hoede, Eds., pp. 71-74.
-
(1997)
Proceedings of the 5th Twente Workshop on Graphs and Combinatorial Optimization
, pp. 71-74
-
-
Eisenbeis, C.1
Lelait, S.2
Marmol, B.3
-
12
-
-
0030143433
-
Iterated register coalescing
-
GEORGE, L., AND APPEL, A. W. Iterated register coalescing. ACM Trans. Program. Lang. Syst. 18, 3 (1996), 300-324.
-
(1996)
ACM Trans. Program. Lang. Syst.
, vol.18
, Issue.3
, pp. 300-324
-
-
George, L.1
Appel, A.W.2
-
13
-
-
0343233078
-
Register allocation frameworks for slide-window architecture
-
in Japanese
-
HARAIKAWA, T., SOENO, M., YAMASHITA, Y., AND NAKATA, I. Register allocation frameworks for slide-window architecture. Transactions of Information Processing Society of Japan 39, 9 (1998), 2684-2694. (in Japanese).
-
(1998)
Transactions of Information Processing Society of Japan
, vol.39
, Issue.9
, pp. 2684-2694
-
-
Haraikawa, T.1
Soeno, M.2
Yamashita, Y.3
Nakata, I.4
-
14
-
-
84976845365
-
A register allocation framework based on hierarchical cyclic interval graphs
-
HENDREN, L. J., GAO, G. R., ALTMAN, E. R., AND MUKERJI, C. A register allocation framework based on hierarchical cyclic interval graphs. In Compiler Construction (1992), pp. 176-191.
-
(1992)
Compiler Construction
, pp. 176-191
-
-
Hendren, L.J.1
Gao, G.R.2
Altman, E.R.3
Mukerji, C.4
-
15
-
-
67650066359
-
Register allocation for software pipelining with predication using spiral graph
-
ITOGA, H., HARAIKAWA, T., YAMASHITA, Y., AND TANAKA, J. Register allocation for software pipelining with predication using spiral graph. In Proceedings of the International Symposium on Future Software Technology (ISFST2001) (2001), pp. 58-65.
-
(2001)
Proceedings of the International Symposium on Future Software Technology (ISFST2001)
, pp. 58-65
-
-
Itoga, H.1
Haraikawa, T.2
Yamashita, Y.3
Tanaka, J.4
-
17
-
-
33746095814
-
A global progressive register allocator
-
KOES, D. R., AND GOLDSTEIN, S. A global progressive register allocator. In Proc. PLDI (2006), pp. 204-215.
-
(2006)
Proc. PLDI
, pp. 204-215
-
-
Koes, D.R.1
Goldstein, S.2
-
18
-
-
0042650298
-
Software pipelining: An effecive scheduling technique for VLIW machines
-
LAM, M. S. Software pipelining: an effecive scheduling technique for VLIW machines. In Proc. PLDI (1988), pp. 318-327.
-
(1988)
Proc. PLDI
, pp. 318-327
-
-
Lam, M.S.1
-
19
-
-
0036660095
-
Cluster assignment for high-performance embedded vliw processors
-
LAPINSKII,V. S., JACOME,M. F., AND VECIANA, G. A. D. Cluster assignment for high-performance embedded vliw processors. ACM Trans. Des. Autom. Electron. Syst. 7, 3 (2002), 430-454.
-
(2002)
ACM Trans. Des. Autom. Electron. Syst
, vol.7
, Issue.3
, pp. 430-454
-
-
Lapinskii, V.S.1
Jacome, M.F.2
Veciana, G.A.D.3
-
20
-
-
0026980852
-
Effective compiler support for predicated execution using the hyperblock
-
MAHLKE, S., LIN, D., W.Y., C., HANK, R., AND BRINGMANN, R. Effective compiler support for predicated execution using the hyperblock. In MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture (1992), pp. 45-54.
-
(1992)
MICRO 25: Proceedings of the 25th Annual International Symposium on Microarchitecture
, pp. 45-54
-
-
Mahlke, S.1
Lin, D.W.Y.C.2
Hank, R.3
Bringmann, R.4
-
21
-
-
4243140423
-
Eulerian disjoint paths problem in grid graphs is NP complete
-
MARX, D. Eulerian disjoint paths problem in grid graphs is NPcomplete. Discrete Appl. Math. 143, 1-3 (2004), 336-341.
-
(2004)
Discrete Appl. Math
, vol.143
, Issue.1-3
, pp. 336-341
-
-
Marx, D.1
-
22
-
-
35248884474
-
An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix
-
MEI, B., VERNALDE, S., VERKEST, D., MAN, H. D., AND LAUWEREINS, R. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In Proc. of Field-Programmable Logic and Applications (2003), pp. 61-70.
-
(2003)
Proc. of Field-Programmable Logic and Applications
, pp. 61-70
-
-
Mei, B.1
Vernalde, S.2
Verkest, D.3
Man, H.D.4
Adres, L.R.5
-
23
-
-
0344064938
-
Exploiting loop-level parallelism for coarsegrained reconfigurable architecture using modulo scheduling
-
MEI, B., VERNALDE, S., VERKEST, D., MAN, H. D., AND LAUWEREINS, R. Exploiting loop-level parallelism for coarsegrained reconfigurable architecture using modulo scheduling. IEE Proceedings: Computer and Digital Techniques 150, 5 (2003).
-
(2003)
IEE Proceedings: Computer and Digital Techniques
, vol.150
, Issue.5
-
-
Mei, B.1
Vernalde, S.2
Verkest, D.3
Man, H.D.4
Lauwereins, R.5
-
24
-
-
34547197349
-
Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures
-
PARK, H., FAN, K., KUDLUR,M., AND MAHLKE, S. Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures. In Proc. CASES (2006).
-
(2006)
Proc. CASES
-
-
Park, H.1
Fan, K.2
Kudlur, M.3
Mahlke, S.4
-
25
-
-
41349090027
-
Reducing register ports for higher speed and lower energy
-
PARK, I., POWELL, M. D., AND VIJAYKUMAR, T. N. Reducing register ports for higher speed and lower energy. In MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture (2002), pp. 171-182.
-
(2002)
MICRO 35: Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture
, pp. 171-182
-
-
Park, I.1
Powell, M.D.2
Vijaykumar, T.N.3
-
26
-
-
4344611593
-
Optimistic register coalescing
-
PARK, J., AND MOON, S.-M. Optimistic register coalescing. ACM Trans. Program. Lang. Syst. 26, 4 (2004), 735-765.
-
(2004)
ACM Trans. Program. Lang. Syst.
, vol.26
, Issue.4
, pp. 735-765
-
-
Park, J.1
Moon, S.-M.2
-
27
-
-
0001228239
-
Linear scan register allocation
-
POLETTO, M., AND SARKAR, V. Linear scan register allocation. ACM Trans. Program. Lang. Syst. 21, 5 (1999), 895-913.
-
(1999)
ACM Trans. Program. Lang. Syst.
, vol.21
, Issue.5
, pp. 895-13
-
-
Poletto, M.1
Sarkar, V.2
-
29
-
-
0003015894
-
Scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
-
RAU, B. R., AND GLASER, C. D. Scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In Proc. 20th Annual Workshop on Microprogramming and Microarchitecture (1981), pp. 183-198.
-
(1981)
Proc. 20th Annual Workshop on Microprogramming and Microarchitecture
, pp. 183-198
-
-
Rau, B.R.1
Glaser, C.D.2
-
30
-
-
0026966702
-
Register allocation for software pipelined loops
-
RAU, B. R., LEE, M., TIRUMALAI, P. P., AND SCHLANSKER, M. S. Register allocation for software pipelined loops. In Proc. PLDI (1992), pp. 283-299.
-
(1992)
Proc. PLDI
, pp. 283-299
-
-
Rau, B.R.1
Lee, M.2
Tirumalai, P.P.3
Schlansker, M.S.4
-
31
-
-
84984708191
-
Inter-cluster communication in vliw architectures
-
TERECHKO, A. S., AND CORPORAAL, H. Inter-cluster communication in vliw architectures. ACM Trans. Archit. Code Optim. 4, 2 (2007), 11.
-
(2007)
ACM Trans. Archit. Code Optim
, vol.4
, Issue.2
, pp. 11
-
-
Terechko, A.S.1
Corporaal, H.2
-
32
-
-
3543071393
-
Cyclic register pressure and allocation for modulo scheduled loops
-
April
-
TOUATI, S.-A.-A., AND EISENBEIS, C. Cyclic register pressure and allocation for modulo scheduled loops. Tech. Rep. 4442, INRIA, April 2002.
-
(2002)
Tech. Rep. 4442, INRIA
-
-
Touati, S.-A.-A.1
Eisenbeis, C.2
|