메뉴 건너뛰기




Volumn , Issue , 2008, Pages 151-160

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

Author keywords

Coarsegrained; Placement and routing; Reconfigurable arrays; Register allocation

Indexed keywords

ALLOCATORS; COARSEGRAINED; DSP ARCHITECTURES; PLACEMENT AND ROUTING; RECONFIGURABLE ARRAY; REGISTER ALLOCATION; REGISTER FILES; RETARGETABILITY; STATE OF THE ART;

EID: 80051539788     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1375657.1375678     Document Type: Conference Paper
Times cited : (24)

References (32)
  • 1
    • 70449575202 scopus 로고    scopus 로고
    • Fast code generation for embedded processors with aliased heterogeneous registers
    • AHN, M., AND PAEK, Y. Fast code generation for embedded processors with aliased heterogeneous registers. Trans. on HiPEAC 2, 2 (2007), 40-59.
    • (2007) Trans. on HiPEAC , vol.2 , Issue.2 , pp. 40-59
    • Ahn, M.1    Paek, Y.2
  • 2
    • 84869345560 scopus 로고    scopus 로고
    • Removing communications in clustered microarchitectures through instruction replication
    • ALETÀ, A., CODINA, J. M., GONZÁLEZ, A., AND KAELI, D. Removing communications in clustered microarchitectures through instruction replication. ACM Trans. Archit. Code Optim. 1, 2 (2004), 127-151.
    • (2004) ACM Trans. Archit. Code Optim. , vol.1-2 , pp. 127-151
    • Aletà, A.1    Codina, J.M.2    González, A.3    Kaeli, D.4
  • 6
    • 84976675935 scopus 로고
    • Register allocation via hierarchical graph coloring
    • CALLAHAN, D., AND KOBLENZ, B. Register allocation via hierarchical graph coloring. SIGPLAN Not. 26, 6 (1991), 192-203.
    • (1991) SIGPLAN Not , vol.26 , Issue.6 , pp. 192-203
    • Callahan, D.1    Koblenz, B.2
  • 7
    • 0000291844 scopus 로고
    • Exact solution of large-scale, asymmetric traveling salesman problems
    • CARPANETO, G., DELL'AMICO, M., AND TOTH, P. Exact solution of large-scale, asymmetric traveling salesman problems. ACM Trans. Math. Softw. 21, 4 (1995), 394-409.
    • (1995) ACM Trans. Math. Softw. , vol.21 , Issue.4 , pp. 394-409
    • Carpaneto, G.1    Dell'amico, M.2    Toth, P.3
  • 14
    • 84976845365 scopus 로고
    • A register allocation framework based on hierarchical cyclic interval graphs
    • HENDREN, L. J., GAO, G. R., ALTMAN, E. R., AND MUKERJI, C. A register allocation framework based on hierarchical cyclic interval graphs. In Compiler Construction (1992), pp. 176-191.
    • (1992) Compiler Construction , pp. 176-191
    • Hendren, L.J.1    Gao, G.R.2    Altman, E.R.3    Mukerji, C.4
  • 17
    • 33746095814 scopus 로고    scopus 로고
    • A global progressive register allocator
    • KOES, D. R., AND GOLDSTEIN, S. A global progressive register allocator. In Proc. PLDI (2006), pp. 204-215.
    • (2006) Proc. PLDI , pp. 204-215
    • Koes, D.R.1    Goldstein, S.2
  • 18
    • 0042650298 scopus 로고
    • Software pipelining: An effecive scheduling technique for VLIW machines
    • LAM, M. S. Software pipelining: an effecive scheduling technique for VLIW machines. In Proc. PLDI (1988), pp. 318-327.
    • (1988) Proc. PLDI , pp. 318-327
    • Lam, M.S.1
  • 21
    • 4243140423 scopus 로고    scopus 로고
    • Eulerian disjoint paths problem in grid graphs is NP complete
    • MARX, D. Eulerian disjoint paths problem in grid graphs is NPcomplete. Discrete Appl. Math. 143, 1-3 (2004), 336-341.
    • (2004) Discrete Appl. Math , vol.143 , Issue.1-3 , pp. 336-341
    • Marx, D.1
  • 24
    • 34547197349 scopus 로고    scopus 로고
    • Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures
    • PARK, H., FAN, K., KUDLUR,M., AND MAHLKE, S. Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures. In Proc. CASES (2006).
    • (2006) Proc. CASES
    • Park, H.1    Fan, K.2    Kudlur, M.3    Mahlke, S.4
  • 29
    • 0003015894 scopus 로고
    • Scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
    • RAU, B. R., AND GLASER, C. D. Scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In Proc. 20th Annual Workshop on Microprogramming and Microarchitecture (1981), pp. 183-198.
    • (1981) Proc. 20th Annual Workshop on Microprogramming and Microarchitecture , pp. 183-198
    • Rau, B.R.1    Glaser, C.D.2
  • 30
  • 31
    • 84984708191 scopus 로고    scopus 로고
    • Inter-cluster communication in vliw architectures
    • TERECHKO, A. S., AND CORPORAAL, H. Inter-cluster communication in vliw architectures. ACM Trans. Archit. Code Optim. 4, 2 (2007), 11.
    • (2007) ACM Trans. Archit. Code Optim , vol.4 , Issue.2 , pp. 11
    • Terechko, A.S.1    Corporaal, H.2
  • 32
    • 3543071393 scopus 로고    scopus 로고
    • Cyclic register pressure and allocation for modulo scheduled loops
    • April
    • TOUATI, S.-A.-A., AND EISENBEIS, C. Cyclic register pressure and allocation for modulo scheduled loops. Tech. Rep. 4442, INRIA, April 2002.
    • (2002) Tech. Rep. 4442, INRIA
    • Touati, S.-A.-A.1    Eisenbeis, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.