Low-power functionality enhanced computation architecture using spin-based devices

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Volumn , Issue , 2011, Pages 129-136

  Augustine, Charles ^a   Panagopoulos, Georgios ^a   Behin Aein, Behtash ^a   Srinivasan, Srikant ^a   Sarkar, Angik ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

logic; nanomagnet; Non local spin torque; scaling

Indexed keywords

ACTIVE POWER; ARITHMETIC LOGIC UNIT; BUILDING BLOCKES; CIRCUIT OPERATION; ELECTRON SPINS; GATE-LEAKAGE CURRENT; LOGIC; LOGIC BLOCKS; LOW POWER; NANOMAGNET; NONLOCAL; SCALING; SELF-DUAL; SPIN-BASED DEVICES; SPIN-TORQUE SWITCHING; STAND-BY LEAKAGE; SUBTHRESHOLD;

ADDERS; CMOS INTEGRATED CIRCUITS; DISCRETE COSINE TRANSFORMS; LEAKAGE CURRENTS; LOGIC DEVICES; MULTIPLYING CIRCUITS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; POWER INTEGRATED CIRCUITS; SIGNAL PROCESSING;

LOGIC CIRCUITS;

EID: 79961205210     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2011.5941494     Document Type: Conference Paper

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