Novel dielectric-engineered trapping-charge poly-si-TFT memory with a TiN-alumina-nitride-vacuum-silicon structure

IEEE Electron Device Letters

Volumn 32, Issue 8, 2011, Pages 1095-1097

  Wu, Chun Yu ^a   Liu, Yen Ting ^a   Liao, Ta Chuan ^a   Yu, Ming H ^a   Cheng, Huang Chung ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Field enhanced nanowire (FEN); high ; poly Si; system on panel (SOP); thin film transistors (TFTs); trapping charge memory

Indexed keywords

DEFECT CREATION; FIELD ENHANCEMENT; FIELD-ENHANCED NANOWIRE (FEN); PROGRAM/ERASE; RETENTION CHARACTERISTICS; SYSTEM ON PANEL; TRAPPING-CHARGE MEMORY; TUNNELING OXIDES;

ELECTRIC FIELDS; NANOWIRES; THIN FILM TRANSISTORS; TITANIUM NITRIDE; VACUUM;

FLASH MEMORY;

EID: 79960904129     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2158053     Document Type: Article

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