A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Liao, Ta Chuan ^a   Chen, Sheng Kai ^a   Yu, Ming H ^a   Wu, Chun Yu ^a   Kang, Tsung Kuei ^b   Chien, Feng Tso ^b   Liu, Yen Ting ^a   Lin, Chia Min ^b   Cheng, Huang Chung ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b FENG CHIA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER TUNNELING; CHARGE TRAPPING MEMORIES; GATE-ALL-AROUND; LOCAL ELECTRIC FIELD; LOW-TEMPERATURE POLY-SI; LTPS-TFT; MEMORY WINDOW; NANOWIRE STRUCTURES; NON-VOLATILE MEMORIES; PROCESS SIMPLICITY; PROGRAM AND ERASE; SHARP CORNERS; SIDEWALL SPACER; SILICON OXIDE NITRIDE OXIDE SILICONS; SIMULATION RESULT; SONOS MEMORY; SYSTEM ON PANEL;

ELECTRIC FIELDS; ELECTRIC WIRE; ELECTRON DEVICES; NANOWIRES; NITRIDES; POLYSILICON; SILICON OXIDES; WETLANDS;

THIN FILM TRANSISTORS;

EID: 77952411568     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424387     Document Type: Conference Paper

References (10)

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