Compact lumped element model for TSV in 3D-ICs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 2321-2324

  Salah, Khaled ^a   El Rouby, Alaa ^a   Ragai, Hani ^b   Amin, Karim ^c   Ismail, Yehea ^c  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b AIN SHAMS UNIVERSITY   (Egypt)

^c NILE UNIVERSITY   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; CLOSED-FORM EXPRESSION; CURRENT TECHNOLOGY; DESIGN METHODOLOGY; DEVICE CAPACITANCE; DIMENSIONAL ANALYSIS METHODS; DIRECT EXTRACTION; ELECTROMAGNETIC SIMULATION; GROUND CONTACTS; LUMPED ELEMENT MODEL; OXIDE CAPACITANCE; PARASITIC ELEMENT; PARASITICS; SPICE SIMULATIONS; SUBSTRATE RESISTIVITY; THROUGH-SILICON-VIA; WIDE-BAND;

CAPACITANCE; FIELD EFFECT TRANSISTORS; INDUCTANCE; SCATTERING PARAMETERS; SPICE;

THREE DIMENSIONAL;

EID: 79960871080     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5938067     Document Type: Conference Paper

References (18)

1. C. Ryu, D. Chung, Junho Lee, K. Lee, T. Oh, J. Kim, "High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package," in IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 2005, pp. 151-154.
2. J. Pak, C. Ryu, J. Kim, "Electrical Characterization of Through Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation," in Electromagnetic Electronic Materials and Packaging, 2007.Conf., May.2008, pp. 351-354.
3. Dong Min Jang, Chunghyun Ryu, Kwang Yong Lee, Byeong Hoon Cho, Joungho Kim, Tae Sung Oh, Won Jong Lee, and Jin Yu, "Development and Evaluation of 3- D SiP with Vertically Interconnected Through Silicon Vias (TSV)," in Proc. of ECTC, 2007, pp. 847-852.
4. Soon Wee Ho, Seung Wook Yoon, Qiaoer Zhou, Krishnamachar Pasad, Vaidyanathan Kripesh and John H. Lau, "High RF Performance TSV Silicon Carrier for High Frequency Application," in Electronic Components and Technology Conference, 2008.
5. Joohee Kim, Eakhwan Song, Jeonghyeon Cho, Jun So Pak, Junho Lee, Hyungdong Lee, Kunwoo Park, and Joungho Kim, "Through Silicon Via (TSV) Equalizer," in Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference.
6. M. Rousseau, O. Rozeau, G. Cibrario, G. Le Carval, M.-A. Jaud, P. Leduc, A. Farcy, A. Marty, "Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology," in IMAPS Device Packaging Conference, Phoenix, AZ : United States, 2008.
7. I. Savidis and E. G. Friedman, "Electrical Modeling and Characterization of 3-D Vias," in Proc. IEEE Int. Symp. Circuits Syst., May 2008.
8. Ioannis Savidis and E. G. Friedman, "Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance," IEEE Transactions on Electron Devices, vol. 56, no. 9, September 2009.
9. R. Weerasekera, D. Pamunuwa, M. Grange, H. Tenhunen, and L.-R. Zheng, "Closed-form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits (ICs)," in Proc. Workshop 3-D Integr., DATE Conf., Apr. 2009.
10. Tapobrata Bandyopadhyay, Ritwik Chatterjee, Daehyun Chung, Madhavan Swaminathan and Rao Tummala, "Electrical Modeling of Through Silicon and Package Vias," in 3D System Integration, 2009. 3DIC 2009. IEEE International Conference.
11. Chuan Xu, Hong Li, Roberto Suaya, and Kaustav Baner-jee, "Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs," in IEDM09-521, 2009.
12. Michele Stucchi, Kristin De Meyer, and Wim Dehaene, Senior Guruprasad Katti, "Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs," IEEE Transactions on Electron Devices, vol. 57, no. 1, January 2010.
13. http://www.ansoft.com/products/si/hfss.
14. http://www.ansoft.com/products/si/q3d extractor.
15. S. M. Sze and Kwok Kwok Ng, "Physics of semiconductor devices"Wiley, John & Sons, Inc., October 2006.
16. Y.L.Chow and M.M.A. Salama, "A Simplified Method for Calculating the Substation Grounding Grid Resistance," Power Delivery, IEEE Transactions, pp. 736 - 742, April 1994.
17. T. Szirtes, Applied Dimensional Analysis and Modeling. New York: McGraw-Hill, 1997.
18. http://www.matlab.com.