DC characteristics of Junction Vertical Slit Field-Effect Transistor (JVeSFET)

Proceedings of the 16th International Conference - Mixed Design of Integrated Circuits and Systems, MIXDES 2009

Volumn , Issue , 2009, Pages 420-423

  Pfitzner, Andrzej ^a   Staniewski, Michał ^a   Strzyga, Michał ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

JFET; JVeSFET; Vertical slit transistor integrated circuit

Indexed keywords

DC CHARACTERISTICS; DEEP SUB-MICRON; DUAL GATES; FEASIBILITY STUDIES; JFET; JVESFET; LAYOUT REGULARITY; NANO-SIZE; SIMULATION-BASED;

FIELD EFFECT TRANSISTORS; RESOURCE ALLOCATION;

INTEGRATED CIRCUITS;

EID: 72149115395     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. L. Blanquart et al., "Study of proton radiation effects on analog IC designed for high energy physics in a BiCMOS-JFET radhard SOI technology", IEEE Trans. on Nucl. Sci., vol. 41 (6), pp. 2525-2529, December 1994.
2. M. Dentan et al., "Industrial transfer and stabilization of a CMOS-JFETbipolar radiation-hard analog-digital SOI technology", IEEE Trans. on Nucl. Sci., vol. 46 (4), pp. 822-828, August 1999.
3. Y. Fu, H. Wong, and J. J. Liou, "Characterization and modelling of flicker noise in junction field-effect transistor with source and drain trench isolation", Microelectronics Reliab., vol. 47, pp. 46-50, 2007.
4. W. Maly, "Integrated Circuit Fabrication and Associated Methods, Devices and Systems ", U.S. Non-Provisional Patent Application Serial Number CMU Docket 06-091; DMC Docket 06-001PCTCMU.
5. W. Maly, and A. Pfitzner, " Complementary Vertical Slit Field Effect Transistors ", Carnegie Mellon University, Techreport No. CSSI 08-02, 01/2008.
6. W. W. Wong, and J. J. Liou, "Two-dimensional analysis of ion-implanted, bipolar-compatible, long- and short-channel junction field-effect transistors", IEEE Trans. On Electron Dev., vol. 39 (11), pp. 2576-2582, November 1992.