A 400-nW 19.5-fJ/conversion-step 8-ENOB 80-kS/s SAR ADC in 0.18-μm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 58, Issue 7, 2011, Pages 407-411

  Cheong, Jia Hao ^a   Chan, Kok Lim ^b   Khannur, Pradeep Basappa ^a   Tiew, Kei Tee ^a   Je, Minkyu ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b INSTITUTE FOR INFOCOMM RESEARCH   (Singapore)

Author keywords

Common mode reset; redundant algorithm; successive approximation analog to digital converter (SAR ADC); time domain comparator; trilevel switching; ultralow power

Indexed keywords

APPROXIMATION ALGORITHMS; APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPARATORS (OPTICAL); ELECTRIC POWER UTILIZATION; ENERGY GAP; FREQUENCY CONVERTERS; LOW POWER ELECTRONICS; MEDICAL APPLICATIONS; SECONDARY BATTERIES; SENSOR NODES; SIGNAL TO NOISE RATIO; SWITCHING; WIRELESS CHARGING;

COMMON MODE; EFFECTIVE NUMBER OF BITS; IMPLANTABLE MEDICAL DEVICES; SIGNAL TO NOISE AND DISTORTION RATIO; SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS; TIME DOMAIN; ULTRA-LOW POWER; ULTRA-LOW POWER CONSUMPTION;

ANALOG TO DIGITAL CONVERSION;

EID: 79960730138     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2011.2158255     Document Type: Article

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