SAR ADC algorithm with redundancy

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 268-271

  Ogawa, Tomohiko ^a   Kobayashi, Haruo ^a   Hotta, Masao ^b   Takahashi, Yosuke ^a   San, Hao ^a   Takai, Nobukazu ^a  

^a GUNMA UNIVERSITY   (Japan)

^b TOKYO CITY UNIVERSITY   (Japan)

Author keywords

Digital error correction; Non binary; Redundancy; SAR ADC

Indexed keywords

BINARY SEARCH ALGORITHMS; DECISION ERRORS; DIGITAL ERROR CORRECTION; NON-BINARY; SAR ADC; SUCCESSIVE APPROXIMATION REGISTERS;

APPROXIMATION ALGORITHMS; ERROR CORRECTION; LEARNING ALGORITHMS; MULTICARRIER MODULATION; QUALITY ASSURANCE; REDUNDANCY;

SYNTHETIC APERTURES;

EID: 62949243328     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4746011     Document Type: Conference Paper

References (5)

1. ISSCC Short Course, Automotive Technology and Circuits (Feb. 2005).
2. M. Hotta, A. Hayakawa, N. Zhao, Y. Takahashi, H. Kobayashi, "SAR ADC Architecture with Digital Error Correction", IEEJ International Analog VLSI Workshop, Hangzhou, China (Nov. 2006).
3. S. Shimokura, M. Hotta, Y. Takahashi, H. Kobayashi, "Conversion Rate Improvement of SAR ADC with Digital Error Correction," IEEJ International Analog VLSI Workshop, Limerick, Ireland (Nov. 2007).
4. M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske, "A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13μm CMOS," Tech. Digest of ISSCC (Feb. 2007).
5. F. Kuttner, "A 1.2V 10b 20MS/S Non-Binary Successive Approximation ADC in 0.13μm CMOS," Tech. Digest of ISSCC (Feb. 2002).