Chip level reliability of MANOS cells under operating conditions

2009 IEEE International Memory Workshop, IMW '09

Volumn , Issue , 2009, Pages

  Choi, Eun Seok ^a   Kim, Se Jun ^a   Seo, Soon Ok ^a   Yoo, Hyun Seung ^a   Park, Kyoung Hwan ^a   Jung, Sung Wook ^a   Lim, Se Yun ^a   Joo, Han Soo ^a   Kim, Gyo Ji ^a   Lee, Sang Bum ^a   Oh, Sang Hyun ^a   Om, Jae Chul ^a   Yi, Jeong Hyong ^a   Lee, Seok Kiu ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CELL ARRAY; CHIP-LEVEL; LOSS RATES; OPERATING CONDITION; SHALLOW TRAPS;

NITRIDES;

CELL MEMBRANES;

EID: 70349986906     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2009.5090584     Document Type: Conference Paper

References (5)

1. H. Tanaka et. al., Symposium on VLSI Technology, pp.14-15, 2007.
2. Choi et. al., IEEE NVSMW, pp. 83-84, 2007.
3. Lee et. al., IEEE NVSMW, pp. 54-55, 2006.
4. Y. Wang and M.H. White, Solid-State Elec., Vol. 49(1), pp. 97-107, 2005.
5. Kim et. al., Appl. Phys. Lett., Vol. 92, 132901, 2008