25nm 64Gb 130mm2 3bpc NAND flash memory

2011 3rd IEEE International Memory Workshop, IMW 2011

Volumn , Issue , 2011, Pages

  Goldman, M ^a   Pangal, K ^a   Naso, G ^b   Goda, A ^b  

^a INTEL CORPORATION   (United States)

^b MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY ARCHITECTURE; BUSINESS REQUIREMENT; DIE SIZE; NAND FLASH MEMORY; PROCESS TECHNOLOGIES; TECHNOLOGY-BASED;

MEMORY ARCHITECTURE; NAND CIRCUITS;

FLASH MEMORY;

EID: 79959935863     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2011.5873197     Document Type: Article

References (10)

1. Gartner Inc., "Gartner Says Worldwide Semiconductor Revenue to Grow 31.5 Percent in 2010", Sep. 9th, 2010.
2. K. Prall & K. Parat, "25nm 64Gb MLC NAND Technology and Scaling Challenges", IEEE International Electron Device Meeting (IEDM), Dec. 2010.
3. G.G. Marotta, et al., "A 3bit/Cell 32Gb NAND Flash memory at 34nm with 6MB/s Program Throughput and with Dynamic 2b/Cell Blocks Configuration Mode for a Program Throughput Increase up to 13MB/s", ISSCC Dig. Tech. Papers, pp. 444-446, Feb. 2010.
4. R. Zeng, et al., "A 172mm∧2 32Gb MLC NAND Flash Memory in 34nm CMOS", ISSCC Dig. Tech. Papers, pp. 236-237, Feb. 2009.
5. R. Cernea, et al., "A 34MB/s-Program-Throughpu 16Gb MLC NAND with All-Bitline Architecture in 56nm", ISSCC Dig. Tech. Papers, pp. 420-422, Feb. 2008.
6. G. Wong, Applications for Three and Four bit per cell NAND Flash Memories, Report No. FI-NFL-MBC-0210, Forward Insights, pp. 22-23, Feb. 2010.
7. H. P. Belgal, et. al., "A new reliability model for post-cycling charge retention of flash memories", Reliability Physics Symposium Proceedings, pp. 7-20, Aug. 2002 (Pubitemid 34668914)
8. C. Compagnoni, et. al., "First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming", IEDM Tech. Digest, Dec. 2007.
9. C. Compagnoni, et. al., "Random Telegraph Noise Effect on the Programmed Threshold-Voltage Distribution of Flash Memories", IEEE Electron Device Letters, vol. 30, No. 9, pp. 984-986, Sept. 2009.
10. A. Ghetti, et. al., "Scaling trends for random telegraph noise in decananometer Flash memories", IEDM Tech. Digest, Dec. 2008.