A 34MB/s-program-throughput 16Gb MLC NAND with all-bitline architecture in 56nm

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 420-624

  Cernea, Raul ^a   Pham, Long ^a   Moogat, Farookh ^a   Chan, Siu ^a   Le, Binh ^a   Li, Yan ^a   Tsao, Shouchang ^a   Tseng, Tai Yuan ^a   Nguyen, Khanh ^a   Li, Jason ^a   Hu, Jayson ^a   Park, Jong ^a   Hsu, Cynthia ^a   Zhang, Fanglin ^a   Kamei, Teruhiko ^a   Nasu, Hiroaki ^a   Kliza, Phil ^a   Htoo, Khin ^a   Lutze, Jeffrey ^a   Dong, Yingda ^a   Higashitani, Masaaki ^a   Yang, Junhui ^a   Lin, Hung Szu ^a   Sakhamuri, Vamshi ^a   Li, Alan ^a   Pan, Feng ^a   Yadala, Sridhar ^a   Taigor, Subodh ^a   Pradhan, Kishan ^a   Lan, James ^a   Chan, James ^a   Abe, Takumi ^b   Fukuda, Yasuyuki ^b   Mukai, Hideo ^b   Kawakami, Koichi ^b   Liang, Connie ^a   Ip, Tommy ^a   Chang, Shu Fen ^a   Lakshmipathi, Jaggi ^a   Huynh, Sharon ^a   Pantelakis, Dimitris ^a   Mofidi, Mehrdad ^a   Quader, Khandker ^a   more..

^a SanDisk Corporation   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; NAND CIRCUITS;

4-STATE; ALL BITLINE; MEMORY CELL; NAND FLASH MEMORY; PERFORMANCE ENHANCEMENTS; THROUGHPUT RATE; WORDLINES;

MEMORY ARCHITECTURE;

EID: 49549114895     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523236     Document Type: Conference Paper

References (2)

1. 2 8Gb Multi-Level NAND Flash Memory with 10MB/s Program Throughput," ISSCC Dig Tech. Papers, pp.144-145, Feb, 2006.
2. R. Cernea, D. Lee, M. Mofidi et al., "A 34Mb 3.3V Serial Flash EEPROM for Solid-State Disk Applications," ISSCC Dig. Tech Papers, pp.126-127, Feb. 1995.