Low power flip-flop with clock gating on master and slave latches

Electronics Letters

Volumn 36, Issue 4, 2000, Pages 294-295

  Strollo, A G M ^a   De Caro, D ^a  

^a UNIVERSITY OF NAPLES FEDERICO II   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

TIMING CIRCUITS; TRIGGER CIRCUITS;

CLOCK GATING;

FLIP FLOP CIRCUITS;

EID: 0033875370     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000268     Document Type: Article

References (3)

1. CHANDRAKASAN, A.P., SHENG, S., and BRODERSEN, R.W.: 'Low-power CMOS digital design', IEEE J. Solid-State Circuits, 1992, SC-27, (4), pp. 473-484
2. NOGAWA, M., and OHTOMO, Y.: 'A data-transition look-ahead DFF circuit for statistical reduction in power consumption', IEEE J. Solid-State Circuits, 1998, 33, (5), pp. 702-706
3. LANG, T., MUSOLL, F., and CORTADELLA, J.: 'Individual flip-flops with gated clocks for low power datapaths', IEEE Trans. Circuits Syst. II, 1997, 44, (6), pp. 507-516