KL-Cuts: A new approach for logic synthesis targeting multiple output blocks

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 777-782

  Osvaldo Jr , Martinello ^a   Marques, Felipe S ^a   Ribas, Renato P ^a   Reis, André I ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

AIG; Cut enumeration; Technology mapping

Indexed keywords

COVERING ALGORITHMS; LOGIC SYNTHESIS; MULTIPLE OUTPUTS; NEW APPROACHES; TECHNOLOGY MAPPING;

SYNTHESIS (CHEMICAL);

COMPUTATION THEORY;

EID: 77953103647     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Ling, A. C., Zhu, J., "Scalable Synthesis and Clustering Techniques Using Decision Diagrams", IEEE Trans. on CAD. 2008.
2. Mishchenko, A., Brayton, R., "Scalable Logic Synthesis using a Simple Circuit Structure", Int'l Workshop on Logic & Synthesis, 2006. http://www.eecs.berkeley.edu/~alanmi/publications/2006/iwls06-sls.pdf
3. Cong J., Wu, C., Ding, Y., "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution", Int'l Symp. on FPGA, 1999.
4. Pan, P., Lin C., "A New Retiming-based Technology Mapping Algorithm for LUT-based FPGAs", Int'l Symp. on FPGA, 1998.
5. Mishchenko, A., Chatterjee, S., Brayton, R., "DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis", Design Automation Conference, 2006.
6. Mishchenko, A., Brayton, R., Chatterjee, S., "Boolean Factoring and Decomposition of Logic Networks", Int'l Conf. on CAD, 2008.
7. Chatterjee, S., Mishchenko, A. and Brayton, R., "Factor Cuts", Int'l Conf. on CAD, 2006.
8. Werber, J., Rautenbach, D., Szegedy, C., "Timing Optimization by Restructuring Long Combinatorial Paths", Int'l Conf. on CAD, 2007.
9. Rosiello, A. P. E., Ferrandi, F., Pandini, D., Sciuto, D., "A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis", IEEE Comp. Soc. Annual Symp. on VLSI, 2007.
10. Mishchenko, A., Chatterjee, S., Brayton, R., "Improvements to Technology Mapping for LUT-Based FPGAs", Int'l Symp. on FPGA, 2006.
11. Berkeley Logic Synthesis and Verification Group, "ABC: A System for Sequential Synthesis and Verification". http://www.eecs.berkeley.edu/ ~alanmi/abc
12. Xilinx, "Achieving Higher System Performance with the Virtex-5 Family of FPGAs", White Paper, 2006. http://www.xilinx.com/
13. Altera, "Improving FPGA Performance and Area Using an Adaptive Logic Module", White Paper, 2004. http://www.altera.com/
14. Mishchenko, A., Brayton, R., Jiang, J. H. R., Jang, S., "Scalable Don't-Care-Based Logic Optimization and Resynthesis", Int'l Symp. on FPGA, 2009.