Automatic state space decomposition for approximate FSM traversal based on circuit analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1451-1464

  Cho, Hyunwoo ^a   Hachtel, Gary D ^a   Macii, Enrico ^a   Poncino, Massimo ^a   Somenzi, Fabio ^a  

^a UCB 450   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION THEORY; ELECTRIC NETWORK ANALYSIS; FINITE AUTOMATA; FLIP FLOP CIRCUITS; GRAPH THEORY; HEURISTIC METHODS; OPTIMIZATION; STATE SPACE METHODS;

AUTOMATIC STATE SPACE DECOMPOSITION; LATCH CONNECTIVITY; LATCH CORRELATION;

SEQUENTIAL CIRCUITS;

EID: 0030405069     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552079     Document Type: Article

References (17)

1. O. Coudert, C. Berthet, J. C. Madre, "Verification of sequential machines using Boolean functional vectors," in IFIP Int. Wkshp. Applied Formal Methods for Correct VLSI Design, Leuven, Belgium, Nov. 1989, pp. 111-128.
2. R. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput.. vol. C-35, pp. 79-85, Aug. 1986.
3. K. S. Brace, R. Rudell, and R. Bryant, "Efficient implementation of a BDD package," in DAC-27: ACM/IEEE Design Automation Conf., Orlando, FL, June 1990, pp. 40-45.
4. J. R. Burch, E. M. Clarice, K. L. McMillan, and D. L. Dill, "Sequential circuit verification using symbolic model checking," in DAC-27: ACM/IEEE Design Automation Conf.. Orlando, FL, June 1990, pp. 46-51.
5. O. Coudert and J. C. Madre, "A unified framework for the formal verification of sequential circuits," in ICCAD-90: IEEE Int. Conf. Computer-Aided Design. Santa Clara, CA, Nov. 1990, pp. 126-129.
6. H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. SangiovanniVincentelli, "Implicit enumeration of finite state machines using BDD's," in ICCAD-90: IEEE Int. Conf. Computer-Aided Design. Santa Clara, CA, Nov. 1990, pp. 130-133.
7. H. Cho, G. D. Hachtel, S. W. Jeong, B. Plessier, E. Schwarz, and F. Somenzi, "ATPG aspects of FSM verification," in ICCAD-90: IEEE Int. Conf. Computer-Aided Design, pp. 134-137, Santa Clara, CA, Nov. 1990.
8. J. R. Burch, E. M. Clarice, and D. E. Long, "Representing circuits more efficiently in symbolic model checking," in DAC-28: ACM/IEEE Design Automation Conf., San Francisco, CA, June 1991, pp. 403-407.
9. H. Cho, G. D. Hachtel, E. Macii, B. Plessier, and F. Somenzi, "Algorithms for approximate FSM traversal based on state space decomposition," this issue, pp. 1465-1478.
10. F. Brglez, D. Bryan.and K. Kozmiriski, "Combinational profiles of sequential benchmark circuits," in ISCAS-89: IEEE Int. Symp. Circuits Syst.. Portland, OR, May 1989, pp. 1929-1934.
11. H. Cho, G. D. Hachtel, and F. Somenzi, "Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration," IEEE Trans. Computer-Aided Design, vol. 12, pp. 935-945, July 1993.
12. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, second ed. New York: W. H. Freeman, 1979.
13. B. W. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs," Bell Syst. Tech. ]., vol. 49, pp. 291-307, Feb. 1970.
14. R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "MIS: A multiple-level interactive logic optimization system," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1062-1081, Nov. 1987.
15. S. Yang, "Logic synthesis and optimization benchmarks User Guide Version3.0," Tech. Rep. MCNC, Jan. 1991.
16. S. Panda, F. Somenzi, and B. Plessier, "Symmetry detection and dynamic variable ordering of decision diagrams," in ICCAD-94: ACM/IEEE Int. Conf. Computer-Aided Design. San Jose, CA, Nov. 1994, pp. 628-631.
17. H. Cho, G. D. Hachtel, E. Macii, M. Poncino, K. Ravi, and F. Somenzi, "Approximate finite state machine traversal: Extensions and new results," in IWLS-95: ACM/IEEE 1995 Int. Wkshp. Logic Synthesis. Session3, Lake Tahoe, NV, May 1995, pp. 3.1-3.5.