-
1
-
-
66749179303
-
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
-
K. Constantinides, O. Mutlu, and T. Austin, "Online design bug detection: RTL analysis, flexible mechanisms, and evaluation," in IEEE/ACM International Symposium on Microarchitecture, 2008, pp. 282-293.
-
(2008)
IEEE/ACM International Symposium on Microarchitecture
, pp. 282-293
-
-
Constantinides, K.1
Mutlu, O.2
Austin, T.3
-
3
-
-
0036575031
-
Design for debug: Catching design errors in digital chips
-
B. Vermeulen and S. K. Goel, "Design for debug: catching design errors in digital chips," IEEE Design & Test of Computers, vol. 19, pp. 35-43, 2002.
-
(2002)
IEEE Design & Test of Computers
, vol.19
, pp. 35-43
-
-
Vermeulen, B.1
Goel, S.K.2
-
4
-
-
67249116418
-
Debug War Stories
-
L. Winemberg, D. Carder, M. Adadir, R. Aitken, R. Antley, and J. Carulli, "Debug War Stories," in IEEE International Test Conference (ITC), 2008, pp. 1-1.
-
(2008)
IEEE International Test Conference (ITC)
, pp. 1-1
-
-
Winemberg, L.1
Carder, D.2
Adadir, M.3
Aitken, R.4
Antley, R.5
Carulli, J.6
-
8
-
-
45149134835
-
Overview of Debug Standardization Activities
-
B. Vermeulen, R. Kuhnis, J. Rearick, N. Stollon, and G. Swoboda, "Overview of Debug Standardization Activities," Design & Test of Computers, IEEE, vol. 25, pp. 258-267, 2008.
-
(2008)
Design & Test of Computers, IEEE
, vol.25
, pp. 258-267
-
-
Vermeulen, B.1
Kuhnis, R.2
Rearick, J.3
Stollon, N.4
Swoboda, G.5
-
9
-
-
49749144866
-
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation
-
H. F. Ko and N. Nicolici, "Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation," in Proceedings Design, Automation and Test in Europe Conference (DATE), 2008, pp. 1298-1303.
-
(2008)
Proceedings Design, Automation and Test in Europe Conference (DATE)
, pp. 1298-1303
-
-
Ko, H.F.1
Nicolici, N.2
-
10
-
-
39749117563
-
On using lossless compression of debug data in embedded logic analysis
-
ITC
-
E. Anis and N. Nicolici, "On using lossless compression of debug data in embedded logic analysis," in Proceedings IEEE International Test Conference (ITC), 2007, pp. 1-10.
-
(2007)
Proceedings IEEE International Test Conference
, pp. 1-10
-
-
Anis, E.1
Nicolici, N.2
-
11
-
-
51449121174
-
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
-
Y. Joon-Sung and N. A. Touba, "Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture," in Proceedings IEEE VLSI Test Symposium (VTS), 2008, pp. 345-351.
-
(2008)
Proceedings IEEE VLSI Test Symposium (VTS)
, pp. 345-351
-
-
Joon-Sung, Y.1
Touba, N.A.2
-
12
-
-
85165853485
-
-
M. Abramovici, P. Bradley, K. Dwarakanath, P. A. L. P. Levin, G. A. M. G. Memmi, and D. A. M. D. Miller, A reconfigurable design-for-debug infrastructure for SoCs, in Proceedings ACM/IEEE Design Automation Conference (DAC), 2006, pp. 7-12.
-
M. Abramovici, P. Bradley, K. Dwarakanath, P. A. L. P. Levin, G. A. M. G. Memmi, and D. A. M. D. Miller, "A reconfigurable design-for-debug infrastructure for SoCs," in Proceedings ACM/IEEE Design Automation Conference (DAC), 2006, pp. 7-12.
-
-
-
-
13
-
-
0002677861
-
MicroSPARCTM: A case-study of scan based debug
-
ITC
-
K. Holdbrook, S. Joshi, S. Mitra, J. Petolino, R. Raman, and M. Wong, "MicroSPARCTM: a case-study of scan based debug," in Proceedings IEEE International Test Conference (ITC), 1994, pp. 70-75.
-
(1994)
Proceedings IEEE International Test Conference
, pp. 70-75
-
-
Holdbrook, K.1
Joshi, S.2
Mitra, S.3
Petolino, J.4
Raman, R.5
Wong, M.6
-
14
-
-
67249084658
-
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs
-
H. F. Ko, A. B. Kinsman, and N. Nicolici, "Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs," in Proceedings IEEE International Test Conference (ITC), 2008, pp. 1-10.
-
(2008)
Proceedings IEEE International Test Conference (ITC)
, pp. 1-10
-
-
Ko, H.F.1
Kinsman, A.B.2
Nicolici, N.3
-
15
-
-
0024913805
-
Combinational profiles of sequential benchmark circuits
-
F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proceedings IEEE International Symposium on Circuits and Systems (ISCAS), 1989, pp. 1929-1934.
-
(1989)
Proceedings IEEE International Symposium on Circuits and Systems (ISCAS)
, pp. 1929-1934
-
-
Brglez, F.1
Bryan, D.2
Kozminski, K.3
|