Scratchpad memory optimizations for digital signal processing applications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 974-979

  Gilani, Syed Z ^a   Kim, Nam Sung ^a   Schulte, Michael ^b  

^a University of Wisconsin Madison   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; AREA REDUCTION; CELL SIZE; DIE AREA; DIGITAL SIGNALS; DSP APPLICATION; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ERROR TOLERANT; FAILURE RATE; HIGH INTEGRATION DENSITY; LEAKAGE POWER; LOW-YIELD; MEAN ERRORS; MEMORY CAPACITY; ON CHIP MEMORY; ON CHIPS; OPERATING VOLTAGE; POWER CONSUMPTION; POWER SAVINGS; PROCESS VARIATION; RECONFIGURABLE MEMORY; SCRATCH PAD MEMORY; SRAM CELL; VIDEO DECODING; VOLTAGE-SCALING; WORD LENGTH;

COMPUTER GRAPHICS; DESIGN; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSORS; MULTIMEDIA SERVICES; SIGNAL PROCESSING;

STATIC RANDOM ACCESS STORAGE;

EID: 79957576757     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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