-
4
-
-
33645581546
-
Integrated, comprehensive assertion-based coverage
-
J. Sordoillet, S. Davey "Integrated, comprehensive assertion-based coverage", EDA Tech Forum 3(1), pp. 22-25
-
EDA Tech Forum
, vol.3
, Issue.1
, pp. 22-25
-
-
Sordoillet, J.1
Davey, S.2
-
5
-
-
77954565055
-
Defining and providing coverage for assertion-based dynamic verification
-
J. G. Tong, M. Boulé, Z. Zilic, "Defining and Providing Coverage for Assertion-Based Dynamic Verification", J. Electronic Testing 26(2), 2010, pp. 211-225
-
(2010)
J. Electronic Testing
, vol.26
, Issue.2
, pp. 211-225
-
-
Tong, J.G.1
Boulé, M.2
Zilic, Z.3
-
6
-
-
42649094815
-
Accelerating assertion coverage with adaptive testbenches
-
DOI 10.1109/TCAD.2008.917975, 4492842
-
B. Pal, A. Banerjee, A. Sinha, P. Dasgupta, "Accelerating assertion coverage with adaptive testbenches", IEEE Trans Comput-Aided Des Integr Circuits Syst 27(5), 2008, pp. 967-972 (Pubitemid 351596178)
-
(2008)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.27
, Issue.5
, pp. 967-972
-
-
Pal, B.1
Banerjee, A.2
Sinha, A.3
Dasgupta, P.4
-
7
-
-
79955974465
-
-
Mentor Graphics Inc. ModelSim website
-
Mentor Graphics Inc., ModelSim website [http://model. com/]
-
-
-
-
8
-
-
0020593269
-
Test generation for digital systems on the vector alternative graph model
-
R. Ubar, "Test Generation for Digital Systems on the Vector Alternative Graph Model", Proc. of the 13th Symposium on Fault Tolerant Computing", Milano, Italy, 1983, pp. 374-377 (Pubitemid 13593690)
-
(1983)
Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)
, pp. 374-377
-
-
Ubar, R.1
-
9
-
-
0022769976
-
Graph-based algorithms for Boolean function manipulation
-
R. Bryant. "Graph-based algorithms for Boolean function manipulation", IEEE Transactions on Computers, C-35, 8, 1986, pp. 677-691 (Pubitemid 16629996)
-
(1986)
IEEE Transactions on Computers
, vol.C-35
, Issue.8
, pp. 677-691
-
-
Bryant, R.E.1
-
10
-
-
0033700096
-
Back-tracing and event-driven techniques in high-level simulation with decision diagrams
-
R. Ubar, J. Raik, A. Morawiec, "Back-tracing and Event-driven Techniques in High-level Simulation with Decision Diagrams", ISCAS 2000, Vol. 1, pp. 208-211
-
(2000)
ISCAS
, vol.1
, pp. 208-211
-
-
Ubar, R.1
Raik, J.2
Morawiec, A.3
-
11
-
-
73349119660
-
PSL assertion checking using temporally extended high-level decision diagrams
-
Springer Science
-
M. Jenihhin, J. Raik, A. Chepurov, R. Ubar, "PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams", J. of Electronic Testing: Theory and Applications (JETTA), 25(6), 2009, Springer Science, pp. 289-300
-
(2009)
J. of Electronic Testing: Theory and Applications (JETTA)
, vol.25
, Issue.6
, pp. 289-300
-
-
Jenihhin, M.1
Raik, J.2
Chepurov, A.3
Ubar, R.4
-
12
-
-
79955958131
-
-
APRICOT verification framework website
-
APRICOT verification framework website [http://apricot. pld. ttu. ee]
-
-
-
-
13
-
-
79955968965
-
Simulation-based verification with APRICOT framework using high-level decision diagrams
-
Moscow, Sept. 18-21
-
M. Jenihhin, J. Raik, A. Chepurov, R. Ubar. Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams. IEEE East-West Design & Test Symposium, Moscow, Sept. 18-21, 2009, pp. 13-16
-
(2009)
IEEE East-West Design & Test Symposium
, pp. 13-16
-
-
Jenihhin, M.1
Raik, J.2
Chepurov, A.3
Ubar, R.4
-
14
-
-
67649880544
-
High-level decision diagrams based coverage metrics for verification and test
-
Buzios, Brazil March 1-5
-
M. Jenihhin, J. Raik, A. Chepurov, U. Reinsalu, R. Ubar, "High-Level Decision Diagrams based Coverage Metrics for Verification and Test", Proc. of 10th IEEE Latin American Test Workshop, Buzios, Brazil, March 1-5, 2009, pp. 1-6
-
(2009)
Proc. of 10th IEEE Latin American Test Workshop
, pp. 1-6
-
-
Jenihhin, M.1
Raik, J.2
Chepurov, A.3
Reinsalu, U.4
Ubar, R.5
-
15
-
-
0343826160
-
RT-level ITC'99 benchmarks and first ATPG results
-
July-Sept.
-
F. Corno, M. S. Reorda, G. Squillero, "RT-level ITC'99 benchmarks and first ATPG results", Journal, Design & Test of Computers, IEEE, 17(3), July-Sept. 2000, pp. 44-53
-
(2000)
Journal, Design & Test of Computers IEEE
, vol.17
, Issue.3
, pp. 44-53
-
-
Corno, F.1
Reorda, M.S.2
Squillero, G.3
|