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Volumn 26, Issue 2, 2010, Pages 211-225

Defining and providing coverage for assertion-based dynamic verification

Author keywords

Assertions; Automata; Coverage; Test generation; Testing; Verification

Indexed keywords

ASSERTIONS; AUTOMATA; BASED SPECIFICATION; COVERAGE METRICS; DESIGN SPECIFICATION; DYNAMIC VERIFICATIONS; NONDETERMINISTIC AUTOMATA; TEST GENERATIONS; TEST SCENARIO; TEST SEQUENCE;

EID: 77954565055     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-010-5148-9     Document Type: Conference Paper
Times cited : (8)

References (29)
  • 2
    • 77954565092 scopus 로고    scopus 로고
    • EETimes. Available online
    • Anderson TL (2005) Coverage is the heart of verification. EETimes. Available online: http://www.eetimes.com/news/design/features/showArticle.jhtml? articleID=60400630
    • (2005) Coverage Is the Heart of Verification
    • Anderson, T.L.1
  • 4
    • 0035280209 scopus 로고    scopus 로고
    • Efficient detection of vacuity in temporal model checking
    • Beer I, Ben-David S, Eisner C, Rodeh Y (2001) Efficient detection of vacuity in temporal model checking. Form Methods Syst Des 18 (2):141-163
    • (2001) Form Methods Syst. Des. , vol.18 , Issue.2 , pp. 141-163
    • Beer, I.1    Ben-David, S.2    Eisner, C.3    Rodeh, Y.4
  • 6
    • 34548139933 scopus 로고    scopus 로고
    • Adding debug enhancements to assertion checkers for hardware emulation and silicon debug
    • Boulé M, Chenard J, Zilic Z (2006) Adding debug enhancements to assertion checkers for hardware emulation and silicon debug. In: International conference on computer design, pp 294-299
    • (2006) International Conference on Computer Design , pp. 294-299
    • Boulé, M.1    Chenard, J.2    Zilic, Z.3
  • 8
    • 35648929348 scopus 로고    scopus 로고
    • Debug enhancements in assertion-checker generation
    • Boulé M, Chenard J, Zilic Z (2007) Debug enhancements in assertion-checker generation. IET Comput Digit Tech 1 (6):669-677
    • (2007) IET Comput. Digit Tech. , vol.1 , Issue.6 , pp. 669-677
    • Boulé, M.1    Chenard, J.2    Zilic, Z.3
  • 10
    • 40049103424 scopus 로고    scopus 로고
    • Automata-based assertion-checker synthesis of PSL properties
    • Boulé M, Zilic Z (2008) Automata-based assertion-checker synthesis of PSL properties. ACM Transact Des Automat Electron Syst 13 (1):1-21
    • (2008) ACM Transact Des. Automat Electron. Syst. , vol.13 , Issue.1 , pp. 1-21
    • Boulé, M.1    Zilic, Z.2
  • 12
    • 0002263527 scopus 로고
    • Canonical regular expressions and minimal state graphs for definite events
    • Brzozowski J (1962) Canonical regular expressions and minimal state graphs for definite events. Math Theory Automata 12:529-561
    • (1962) Math. Theory Automata , vol.12 , pp. 529-561
    • Brzozowski, J.1
  • 17
    • 68849129610 scopus 로고    scopus 로고
    • Applied assertion-based verification: An industry perspective
    • Foster H (2009) Applied assertion-based verification: an industry perspective. Found Trends Electron Des Autom 3 (1):1-95
    • (2009) Found Trends Electron. Des. Autom , vol.3 , Issue.1 , pp. 1-95
    • Foster, H.1
  • 19
    • 61949111611 scopus 로고    scopus 로고
    • Using formal specifications to support testing
    • Hierons RM, et al (2009) Using formal specifications to support testing. ACM Comput Surv 41 (2):1-76
    • (2009) ACM Comput. Surv , vol.41 , Issue.2 , pp. 1-76
    • Hierons, R.M.1
  • 21
    • 33750896448 scopus 로고    scopus 로고
    • Test generation using SAT-based bounded model checking for validation of pipelined processors
    • GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
    • Koo H-M, Mishra P (2006) Test generation using SAT-based bounded model checking for validation of pipelined processors. In: GLSVLSI '06: proceedings of the 16th ACM Great Lakes symposium on VLSI. ACM, New York, pp 362-365 (Pubitemid 44729277)
    • (2006) Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI , vol.2006 , pp. 362-365
    • Koo, H.-M.1    Mishra, P.2
  • 27
    • 33645581546 scopus 로고    scopus 로고
    • Integrated, comprehensive assertion-based coverage
    • Sordoillet J, Davey S (2006) Integrated, comprehensive assertion-based coverage. EDA Tech Forum 3 (1):22-25
    • (2006) EDA Tech. Forum. , vol.3 , Issue.1 , pp. 22-25
    • Sordoillet, J.1    Davey, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.