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Volumn 1, Issue , 2000, Pages I-208-I-211

Back-tracing and event-driven techniques in high-level simulation with decision diagrams

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PROBLEM SOLVING; RECURSIVE FUNCTIONS;

EID: 0033700096     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.857064     Document Type: Article
Times cited : (15)

References (12)
  • 1
    • 85177106240 scopus 로고    scopus 로고
    • Improving Simulation Efficiency by Hierarchical Abstraction Transformations
    • H. Gruenbacher M. Khosravipour G. Gridling Improving Simulation Efficiency by Hierarchical Abstraction Transformations System Level Design Language Workshop System Level Design Language Workshop Lausanne Switzerland 1998-September
    • (1998)
    • Gruenbacher, H.1    Khosravipour, M.2    Gridling, G.3
  • 3
    • 0031641246 scopus 로고    scopus 로고
    • Hybrid Techniques for Fast Functional Simulation
    • Y. Luo T. Wongsonegoro A. Aziz Hybrid Techniques for Fast Functional Simulation DAC 1998
    • (1998) DAC
    • Luo, Y.1    Wongsonegoro, T.2    Aziz, A.3
  • 4
    • 0029485365 scopus 로고
    • Fast Functional Simulation Using Branching Programs
    • P. Ashar S. Malik Fast Functional Simulation Using Branching Programs ICCAD Conf. 408 412 ICCAD Conf. 1995
    • (1995) , pp. 408-412
    • Ashar, P.1    Malik, S.2
  • 5
    • 33645514915 scopus 로고    scopus 로고
    • Cycle-based Simulation with Decision Diagrams
    • R. Ubar A. Morawiec J. Raik Cycle-based Simulation with Decision Diagrams Design Automation and Test in Europe (DATE) Conference 1999 454 458 Design Automation and Test in Europe (DATE) Conference 1999 München Germany 1999-March-9-12
    • (1999) , pp. 454-458
    • Ubar, R.1    Morawiec, A.2    Raik, J.3
  • 6
    • 0030106765 scopus 로고    scopus 로고
    • Test Synthesis with Alternative Graphs
    • R. Ubar Test Synthesis with Alternative Graphs IEEE Design&Test of Computers 48 57 1996
    • (1996) IEEE Design&Test of Computers , pp. 48-57
    • Ubar, R.1
  • 7
    • 85177127490 scopus 로고    scopus 로고
    • Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation
    • R. Leveugle R. Ubar Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation MIXDES'98 353 358 MIXDES'98 Lodz Poland 1998-June-18-20
    • (1998) , pp. 353-358
    • Leveugle, R.1    Ubar, R.2
  • 8
    • 0032021270 scopus 로고    scopus 로고
    • Combining Functional and Structural Approaches in Test Generation for Digital Systems
    • R. Ubar Combining Functional and Structural Approaches in Test Generation for Digital Systems Microelectron. Reliab. 38 3 317 329 1998
    • (1998) Microelectron. Reliab. , vol.38 , Issue.3 , pp. 317-329
    • Ubar, R.1
  • 9
    • 85177106764 scopus 로고    scopus 로고
    • HLSynth92 benchmark directory at URL http://www.cbl.ncsu.edu/pub/Benchmark_dirs/HLSynth92/
  • 10
    • 85177140055 scopus 로고    scopus 로고
    • FUTEG Benchmakrs
    • E. Gramatova FUTEG Benchmakrs COPERNICUS JEP 9624 FUTEG No9/1995
    • Gramatova, E.1
  • 11
    • 85002037758 scopus 로고    scopus 로고
    • FPGA Design Flow with Automated Test Generation
    • K. H. Diener G. Elst E. Ivask J. Raik R. Ubar FPGA Design Flow with Automated Test Generation Proc. of the 11th Workshop on Test Technology and Reliability of Circuits and Systems 120 123 Proc. of the 11th Workshop on Test Technology and Reliability of Circuits and Systems 1999
    • (1999) , pp. 120-123
    • Diener, K.H.1    Elst, G.2    Ivask, E.3    Raik, J.4    Ubar, R.5
  • 12
    • 85177142819 scopus 로고    scopus 로고
    • High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation
    • J. Raik R. Ubar High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation Proc. of the European Test Workshop Proc. of the European Test Workshop 1999
    • (1999)
    • Raik, J.1    Ubar, R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.