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1
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85177106240
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Improving Simulation Efficiency by Hierarchical Abstraction Transformations
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H. Gruenbacher M. Khosravipour G. Gridling Improving Simulation Efficiency by Hierarchical Abstraction Transformations System Level Design Language Workshop System Level Design Language Workshop Lausanne Switzerland 1998-September
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0031641246
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Hybrid Techniques for Fast Functional Simulation
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Y. Luo T. Wongsonegoro A. Aziz Hybrid Techniques for Fast Functional Simulation DAC 1998
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DAC
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Luo, Y.1
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Aziz, A.3
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0029485365
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Fast Functional Simulation Using Branching Programs
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P. Ashar S. Malik Fast Functional Simulation Using Branching Programs ICCAD Conf. 408 412 ICCAD Conf. 1995
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Ashar, P.1
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33645514915
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Cycle-based Simulation with Decision Diagrams
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R. Ubar A. Morawiec J. Raik Cycle-based Simulation with Decision Diagrams Design Automation and Test in Europe (DATE) Conference 1999 454 458 Design Automation and Test in Europe (DATE) Conference 1999 München Germany 1999-March-9-12
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, pp. 454-458
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Ubar, R.1
Morawiec, A.2
Raik, J.3
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0030106765
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Test Synthesis with Alternative Graphs
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R. Ubar Test Synthesis with Alternative Graphs IEEE Design&Test of Computers 48 57 1996
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IEEE Design&Test of Computers
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Ubar, R.1
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85177127490
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Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation
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R. Leveugle R. Ubar Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation MIXDES'98 353 358 MIXDES'98 Lodz Poland 1998-June-18-20
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Leveugle, R.1
Ubar, R.2
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8
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0032021270
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Combining Functional and Structural Approaches in Test Generation for Digital Systems
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R. Ubar Combining Functional and Structural Approaches in Test Generation for Digital Systems Microelectron. Reliab. 38 3 317 329 1998
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Microelectron. Reliab.
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Ubar, R.1
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9
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85177106764
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HLSynth92 benchmark directory at URL http://www.cbl.ncsu.edu/pub/Benchmark_dirs/HLSynth92/
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10
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85177140055
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FUTEG Benchmakrs
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E. Gramatova FUTEG Benchmakrs COPERNICUS JEP 9624 FUTEG No9/1995
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Gramatova, E.1
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85002037758
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FPGA Design Flow with Automated Test Generation
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K. H. Diener G. Elst E. Ivask J. Raik R. Ubar FPGA Design Flow with Automated Test Generation Proc. of the 11th Workshop on Test Technology and Reliability of Circuits and Systems 120 123 Proc. of the 11th Workshop on Test Technology and Reliability of Circuits and Systems 1999
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Diener, K.H.1
Elst, G.2
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Raik, J.4
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12
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85177142819
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High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation
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J. Raik R. Ubar High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation Proc. of the European Test Workshop Proc. of the European Test Workshop 1999
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(1999)
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Raik, J.1
Ubar, R.2
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