Ultra-low-power and robust digital-signal-processing hardware for implantable neural interface microsystems

IEEE Transactions on Biomedical Circuits and Systems

Volumn 5, Issue 2, 2011, Pages 169-178

  Narasimhan, Seetharam ^a   Chiel, Hillel J ^b   Bhunia, Swarup ^a  

^a Case Western Reserve University   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

implantable biomedical devices; integrated circuit (IC) reliability; low power electronics; Terms Biomedical signal processing

Indexed keywords

APLYSIA CALIFORNICA; BRAIN ACTIVITY; COMPUTATION BLOCKS; CONVENTIONAL DESIGN; DELAY MARGIN; DESIGN APPROACHES; ENERGY REDUCTION; GRACEFUL DEGRADATION; HARDWARE DESIGN; HIGHER FREQUENCIES; IMPLANTABLE BIOMEDICAL DEVICES; IMPLANTABLE MICROSYSTEMS; INTEGRATED-CIRCUIT (IC) RELIABILITY; LOW POWER; MINIATURIZED ELECTRONICS; MULTI-CHANNEL; NEURAL DATA; NEURAL INTERFACES; NEURAL SIGNAL PROCESSING; ON CHIPS; OUTPUT SIGNAL; PARAMETER VARIATION; POWER GATINGS; POWER REDUCTIONS; PROCESS VARIATION; REALTIME PROCESSING; SIMULATION RESULT; SUBTHRESHOLD; TERMS-BIOMEDICAL SIGNAL PROCESSING; TOTAL ENERGY; ULTRA-LOW FREQUENCIES; ULTRA-LOW POWER; UNDER VOLTAGE;

BRAIN; DESIGN; DIGITAL DEVICES; ENERGY DISSIPATION; MICROSYSTEMS; POWER ELECTRONICS; SIGNAL PROCESSING;

ENERGY EFFICIENCY;

EID: 79955876501     PISSN: 19324545     EISSN: None     Source Type: Journal    
DOI: 10.1109/TBCAS.2010.2076281     Document Type: Conference Paper

References (27)

1. K. D. Wise, D. J. Anderson, J. F. Hetke, D. R. Kipke, and K. Na-jafi, "Wireless implantable microsystems: High-density electronic interfaces to the nervous system," Proc. IEEE, vol. 92, no. 1, pp. 76-97, Jan. 2004. (Pubitemid 40890773)
2. B. Chi, J. Yao, S. Han, X. Xie, G. Li, and Z. Wang, "Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications," IEEE Trans. Biomed. Eng., vol. 54, no. 7, pp. 1291-1299, Jul. 2007. (Pubitemid 46956958)
3. R. Harrison, "The design of integrated circuits to observe brain activity," Proc. IEEE, vol. 96, no. 7, pp. 1203-1216, Jul. 2008.
4. R. H. Olsson, III and K. D. Wise, "A three-dimensional neural recording microsystem with implantable data compression circuitry," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2796-2804, Dec. 2005. (Pubitemid 41789174)
5. A. M. Sodagar, K. D. Wise, and K. Najafi, "A fully integrated mixed-signal neural processor for implantable multichannel cortical recording," IEEE Trans. Biomed. Eng., vol. 54, no. 6, pp. 1075-1088, Jun. 2007. (Pubitemid 46815129)
6. T. K. Horiuchi, T. Swindell, D. Sander, and P. Abshire, "A low-power CMOS neural amplifier with amplitude measurements for spike sorting," in Proc. IEEE Int. Symp. Circuits Syst., 2004, vol. 4, pp. 29-32.
7. K. S. Guillory and R. A. Normann, "A 100-channel system for real time detection and storage of extracellular spike waveforms," J. Neurosci. Meth., vol. 91, no. 1-2, pp. 21-29, Sep. 1999. (Pubitemid 29459086)
8. M. Chae, W. Liu, Z. Yang, T. Chen, J. Kim, M. Sivaprakasam, and M. Yuce, "A 128-channel 6 mW wireless neural recording IC with on-the-fly spike sorting and UWB transmitter," in Proc. IEEE Int. Solid-State Circuits Conf., 2008, pp. 146-603.
9. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanism and leakage reduction techniques in deepsubmi-crometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003. (Pubitemid 43779250)
10. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and micro architecture," in Proc. Design Automation Conf., 2003, pp. 338-342.
11. A. P. Chandrakasan, N. Verma, and D. C. Daly, "Ultralow-power electronics for biomedical applications," Annu. Rev. Biomed Eng., vol. 10, pp. 247-274, 2008.
12. S. Narasimhan, H. J. Chiel, and S. Bhunia, "A preferential design approach for energy-efficient and robust implantable neural signal processing hardware," in Proc. 31st Int. Annu. Conf. IEEE Engineering in Medicine and Biology Soc., 2009, pp. 6383-6386.
13. R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, Aug. 1997. (Pubitemid 127559667)
14. S. B. Wilson and R. Emerson, "Spike detection: A review and comparison of algorithms," Clin. Neurophys, vol. 113, pp. 1873-1881, 2002. (Pubitemid 35441054)
15. S. Shahid, J. Walker, and L. S. Smith, "A new spike detection algorithm for extracellular neural recordings," IEEE Trans. Biomed. Eng., vol. 57, no. 4, pp. 853-866, Apr. 2010.
16. S. Narasimhan, M. Cullins, H. J. Chiel, and S. Bhunia, "Wavelet-based neural pattern analyzer for behaviorally significant burst pattern recognition," in Proc. 30th Annu. Int. Conf. IEEE Engineering in Medicine and Biology Soc., 2008, pp. 38-41.
17. R. J. Chandler, S. Gibson, V. Karkare, S. Farshchi, D. Markovic, and J. W. Judy, "A system-level view of optimizing high-channel-count wireless biosignal telemetry," in 31st Annu. Int. Conf. IEEE Engineering in Medicine and Biology Soc., 2009, pp. 5525-5530.
18. G. Strang and T. Nguyen, Wavelets and Filter Banks. Wellesley, MA: Wellesley Cambridge Press, 1996.
19. Matlab Wavelet Toolbox, ver. 2.1, Mathworks. [Online]. Available: http://www.mathworks.com/products/wavelet
20. K. G. Oweiss, A. Mason, Y. Suhail, A. M. Kamboh, and K. E. Thomson, "A scalable wavelet transform VLSI architecture for real-time signal processing in high-density intra-cortical implants," IEEE Trans. Circuits Syst., vol. 54, no. 6, pp. 1266-1278, Jun. 2007. (Pubitemid 46971532)
21. K. K. Parhi and T. Nishitani, "VLSI architectures for discrete wavelet transforms," IEEE Trans. Very Large Scale Integr. Circuits, vol. 1, no. 2, pp. 191-202, Jun. 1993.
22. B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "Analysis and mitigation of variability in subthreshold design," in Proc. Int. Symp. Low Power Electronics and Design, 2005, pp. 20-25. (Pubitemid 41731619)
23. Predictive technology model. [Online]. Available: http://www.eas.asu. edu/~ptm/
24. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Ya-mada, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
25. H. P. Alstad and S. Aunet, "Seven subthreshold flip-flop cells," Norchip, 2007.
26. B. Gosselin, A. E. Ayoub, J.-F. Roy, M. Sawan, F. Lepore, A. Chaud-huri, and D. Guitton, "A mixed-signal multichip neural recording interface with bandwidth reduction," IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 3, pp. 129-141, Sep. 2009.
27. A. M. Kamboh, M. Raetz, K. G. Oweiss, and A. Mason, "Area-power efficient VLSI implementation ofmultichannel DWT for data compression in implantable neuroprosthetics," IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 2, pp. 128-135, Jun. 2007. (Pubitemid 350141713)