Intel pushes lithography limits, co-optimizes design/layout/process at 45nm

Solid State Technology

Volumn 51, Issue 3, 2008, Pages 30-33

  James, Dick ^a  

^a Chipworks ^*  (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHIPWORKS (CO); ELECTRONICS SYSTEMS;

INTEGRATED CIRCUITS; PROFESSIONAL ASPECTS; REVERSE ENGINEERING; TECHNOLOGY TRANSFER;

LITHOGRAPHY;

EID: 41549102138     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (5)

1. K. Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," Proc IEDM, 2007, pp. 247-250; http://download.intel. com/technology/IEDM2007/HiKMG_paper.pdf; http://download.intel.com/technology/iedm2007/ HiKMG_pres.pdf.
2. 2.D. James "An Ongoing History of Strain-Now Available with High-k!" WeSRCH paper http://electronics.wesrch.com/Paper/paper_ details.php?id=ELlSElYJ9AKVU&paper_ type=pdf&type=%20latest.
3. K. Kuhn, "Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS", Proc. IEDM, 2007, pp. 471-474; http://download.intel. com/technology/IEDM2007/ variation.pdf;http:// download.intel.com/technology/IEDM2007/ variation_pres.pdf.
4. D. Bernard et al., "Clear-field Dual Alternating Phase-shift Mask Lithography," Optical Microlithography XV, Proc. SPIE, Vol. 4691, p. 999-1008.
5. S. Rikhiet al., "Design for manufacturing," IDF 2006, session EPRS008.